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* [Sparc] Correctly handle call to functions with ReturnsTwice attribute.Venkatraman Govindaraju2013-09-054-4/+46
| | | | | | | | | | | | In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7) using the stored %fp and register windows. However, this does not guarantee that the longjmp will restore the registers, as they were when the setjmp was called. This is because these registers may be clobbered after returning from setjmp, but before calling longjmp. This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask. llvm-svn: 190033
* [Sparc] Fix an assertion failure while lowering fcmp on long double.Venkatraman Govindaraju2013-09-041-1/+1
| | | | | | | This assertion is triggered because an integer constant is created with wrong type. llvm-svn: 189948
* [Sparc] Add support for soft long double (fp128).Venkatraman Govindaraju2013-09-033-18/+422
| | | | llvm-svn: 189780
* [Sparc] Implement spill and load for long double(f128) registers.Venkatraman Govindaraju2013-09-022-36/+123
| | | | llvm-svn: 189768
* [Sparc] Add long double (f128) instructions to sparc backend. Venkatraman Govindaraju2013-08-255-1/+250
| | | | llvm-svn: 189198
* [Sparc] Added V9's extra floating point registers and their aliases.Venkatraman Govindaraju2013-08-252-1/+58
| | | | llvm-svn: 189195
* Use register masks on SPARC call instructions.Jakob Stoklund Olesen2013-08-232-4/+14
| | | | llvm-svn: 189085
* Add an OtherPreserved field to the CalleeSaved TableGen class.Jakob Stoklund Olesen2013-08-233-2/+13
| | | | | | | | | | This field specifies registers that are preserved across function calls, but that should not be included in the generates SaveList array. This can be used ot generate regmasks for architectures that save registers through other means, like SPARC's register windows. llvm-svn: 189084
* [Sparc] Use HWEncoding instead of unused Num field in Sparc register ↵Venkatraman Govindaraju2013-08-202-12/+9
| | | | | | definitions. Also, correct the definitions of RETL and RET instructions. llvm-svn: 188738
* [Sparc] Enable xword directive in sparcv9.Venkatraman Govindaraju2013-08-101-3/+6
| | | | llvm-svn: 188141
* Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for ↵NAKAMURA Takumi2013-08-061-1/+1
| | | | | | | | | each corresponding CodeGen. Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel. It races to emit *.inc files simultaneously. llvm-svn: 187780
* [Sparc] Rewrite MBB's live-in registers for leaf functions. Also, addVenkatraman Govindaraju2013-07-302-7/+20
| | | | | | | | register i7 as a live-in if current function's return address is taken. This revision fixes PR16269. llvm-svn: 187433
* [Sparc] Use call's debugloc for the unimp instruction.Venkatraman Govindaraju2013-07-301-1/+1
| | | | llvm-svn: 187402
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-3/+3
| | | | | | size. llvm-svn: 186274
* [Sparc]: Add memory operands for the frame references in the storeRegToStackSlotVenkatraman Govindaraju2013-06-261-8/+30
| | | | | | and loadRegFromStackSlot. llvm-svn: 184935
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-222-2/+2
| | | | llvm-svn: 184642
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-5/+7
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-163-31/+0
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc ↵Venkatraman Govindaraju2013-06-087-162/+61
| | | | | | backend. llvm-svn: 183613
* Remember the anyext patterns.Jakob Stoklund Olesen2013-06-071-0/+2
| | | | llvm-svn: 183589
* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-071-0/+3
| | | | llvm-svn: 183587
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-074-9/+10
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183565
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-071-1/+1
| | | | | | I am able to compile/assemble/link/run /bin/echo from FreeBSD. llvm-svn: 183537
* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-073-17/+19
| | | | llvm-svn: 183463
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-4/+4
| | | | | | | Caching it as a pointer allows us to reset it if the TargetMachine object changes. llvm-svn: 183361
* Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,Venkatraman Govindaraju2013-06-0419-154/+157
| | | | llvm-svn: 183243
* Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju2013-06-034-0/+37
| | | | llvm-svn: 183094
* Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2013-06-032-0/+8
| | | | | | using two instructions (sethi and store). llvm-svn: 183090
* Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju2013-06-021-22/+177
| | | | llvm-svn: 183088
* Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju2013-06-021-1/+1
| | | | llvm-svn: 183083
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ↵Venkatraman Govindaraju2013-06-011-0/+6
| | | | | | as non-leaf functions. llvm-svn: 183079
* [Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju2013-06-014-30/+79
| | | | llvm-svn: 183067
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-2/+2
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-291-4/+6
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. llvm-svn: 182885
* SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. ↵NAKAMURA Takumi2013-05-291-1/+1
| | | | | | [-Wunused-function] llvm-svn: 182850
* [Sparc] Add support for leaf functions in sparc backend. Venkatraman Govindaraju2013-05-296-28/+123
| | | | llvm-svn: 182822
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-253-28/+28
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Also expand 64-bit bitcasts.Jakob Stoklund Olesen2013-05-201-0/+2
| | | | llvm-svn: 182229
* Implement spill and fill of I64Regs.Jakob Stoklund Olesen2013-05-201-2/+9
| | | | llvm-svn: 182228
* Mark i64 SETCC as expand so it is turned into a SELECT_CC.Jakob Stoklund Olesen2013-05-201-0/+2
| | | | llvm-svn: 182227
* Don't use %g0 to materialize 0 directly.Jakob Stoklund Olesen2013-05-192-4/+2
| | | | | | | | The wired physreg doesn't work on tied operands like on MOVXCC. Add a README note to fix this later. llvm-svn: 182225
* Select i64 values with %icc conditions.Jakob Stoklund Olesen2013-05-191-0/+5
| | | | llvm-svn: 182224
* Add floating point selects on %xcc predicates.Jakob Stoklund Olesen2013-05-191-0/+10
| | | | llvm-svn: 182222
* Implement SPselectfcc for i64 operands.Jakob Stoklund Olesen2013-05-192-27/+31
| | | | | | | Also clean up the arguments to all the MOVCC instructions so the operands always are (true-val, false-val, cond-code). llvm-svn: 182221
* [Sparc] Rearrange integer registers' allocation order so that register ↵Venkatraman Govindaraju2013-05-192-10/+23
| | | | | | | | allocator will use I and G registers before using L and O registers. Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode. llvm-svn: 182219
* Handle i64 FrameIndex nodes in SPARC v9 mode.Jakob Stoklund Olesen2013-05-191-1/+1
| | | | llvm-svn: 182216
* [Sparc] Implements hasReservedCallFrame and hasFP.Venkatraman Govindaraju2013-05-172-1/+17
| | | | | | | This is to generate correct framesetup code when the function has variable sized allocas. llvm-svn: 182108
* [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay ↵Venkatraman Govindaraju2013-05-161-5/+9
| | | | | | slot. llvm-svn: 182063
* Remove the MachineMove class.Rafael Espindola2013-05-131-0/+1
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Remove unused argument.Rafael Espindola2013-05-102-3/+2
| | | | llvm-svn: 181618
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