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authorVenkatraman Govindaraju <venkatra@cs.wisc.edu>2013-07-30 19:53:10 +0000
committerVenkatraman Govindaraju <venkatra@cs.wisc.edu>2013-07-30 19:53:10 +0000
commitfee76fac2f626baea2e5cc4b69fe3859a53680eb (patch)
tree50c1995f51484f4d983244babbebb5bd118a7bd9 /llvm/lib/Target/Sparc
parent8742add4b1ec0bcf0c503bb8e03e319b549025aa (diff)
downloadbcm5719-llvm-fee76fac2f626baea2e5cc4b69fe3859a53680eb.tar.gz
bcm5719-llvm-fee76fac2f626baea2e5cc4b69fe3859a53680eb.zip
[Sparc] Rewrite MBB's live-in registers for leaf functions. Also, add
register i7 as a live-in if current function's return address is taken. This revision fixes PR16269. llvm-svn: 187433
Diffstat (limited to 'llvm/lib/Target/Sparc')
-rw-r--r--llvm/lib/Target/Sparc/SparcFrameLowering.cpp11
-rw-r--r--llvm/lib/Target/Sparc/SparcISelLowering.cpp16
2 files changed, 20 insertions, 7 deletions
diff --git a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
index 7e91bc38d42..536e466ca3d 100644
--- a/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcFrameLowering.cpp
@@ -188,6 +188,17 @@ void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
MRI.setPhysRegUnused(reg);
}
+ // Rewrite MBB's Live-ins.
+ for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
+ MBB != E; ++MBB) {
+ for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
+ if (!MBB->isLiveIn(reg))
+ continue;
+ MBB->removeLiveIn(reg);
+ MBB->addLiveIn(reg - SP::I0 + SP::O0);
+ }
+ }
+
assert(verifyLeafProcRegUse(&MRI));
#ifdef XDEBUG
MF.verify(0, "After LeafProc Remapping");
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 6ddfa8cc29b..4b0fa67bc51 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1722,20 +1722,22 @@ static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
return FrameAddr;
}
-static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
- MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
+static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
+ const SparcTargetLowering &TLI) {
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
MFI->setReturnAddressIsTaken(true);
EVT VT = Op.getValueType();
SDLoc dl(Op);
- unsigned RetReg = SP::I7;
-
uint64_t depth = Op.getConstantOperandVal(0);
SDValue RetAddr;
- if (depth == 0)
+ if (depth == 0) {
+ unsigned RetReg = MF.addLiveIn(SP::I7,
+ TLI.getRegClassFor(TLI.getPointerTy()));
RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
- else {
+ } else {
// Need frame address to find return address of the caller.
MFI->setFrameAddressIsTaken(true);
@@ -1793,7 +1795,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::FNEG:
case ISD::FABS: return LowerF64Op(Op, DAG);
- case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
+ case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::GlobalTLSAddress:
llvm_unreachable("TLS not implemented for Sparc.");
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