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* Added:Misha Brukman2003-05-302-15/+108
| | | | | | | * ability to save BasicBlock references to be resolved later * register remappings from the enum values to the real hardware numbers llvm-svn: 6449
* Fixed the namespace to match SparcInternals.h; added notes on some missingMisha Brukman2003-05-301-5/+18
| | | | | | sections of instructions. llvm-svn: 6448
* The register types need to be visible outside of the class to be useful.Misha Brukman2003-05-301-14/+13
| | | | | | For one, converting register numbers based on class in the code emitter. llvm-svn: 6447
* Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.Misha Brukman2003-05-302-448/+457
| | | | | | | Code beautification for the rest of the code: changed layout to match the rest of the code base. llvm-svn: 6446
* Make LLI behave just like LLC with regard to the compile passes it uses.Misha Brukman2003-05-301-0/+15
| | | | llvm-svn: 6444
* Made the register and immediate versions of instructions consecutive.Misha Brukman2003-05-301-7/+5
| | | | llvm-svn: 6439
* Because the format of the shift instructions is `shift r, shcnt, r', theMisha Brukman2003-05-301-7/+11
| | | | | | | | | | | | | instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that implies that the two registers are the first two parameters to the instruction. Thus I made the instructions inherit from F3rd again, and manually added an rs1 field AFTER the shcnt field in the instruction, which maps to the appropriate place in the instruction. The other changes are just elimination of unnecessary spaces. llvm-svn: 6437
* Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well.Brian Gaeke2003-05-302-3/+7
| | | | | | | SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also, their fields were totally screwed up. This seems to fix the problem. llvm-svn: 6429
* Since there is now another derived .inc file, ignore them all.Misha Brukman2003-05-291-1/+1
| | | | llvm-svn: 6411
* Use an absolute path to TableGen because not everyone (e.g. automatic tester)Misha Brukman2003-05-291-1/+1
| | | | | | has their path set up by this point. llvm-svn: 6410
* When TableGen finds an error in the SparcV9.td file, it exits with a non-zeroMisha Brukman2003-05-291-1/+4
| | | | | | | | | | | exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only much later, produces a link error because the key function that TableGen creates isn't found. Using a temporary file in the middle forces a good .INC file to be generated by TableGen, and it will keep trying until you fix the input file. llvm-svn: 6392
* Fixed to use the correct format of the instruction.Misha Brukman2003-05-291-3/+3
| | | | llvm-svn: 6390
* This should work better with re-generating the SparcV9CodeEmitter.inc file.Misha Brukman2003-05-291-6/+8
| | | | | | Also, added a rule to delete the generated .inc file on `make clean'. llvm-svn: 6389
* * Broke up SparcV9.td into separate files as it was getting unmanageableMisha Brukman2003-05-295-258/+381
| | | | | | | | * Added some Format 4 classes, but not instructions * Added notes on missing sections with FIXMEs * Added RDCCR instr llvm-svn: 6388
* Fixed ordering of elements in instructions: although the binary instructionsMisha Brukman2003-05-281-30/+50
| | | | | | | | | | | list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is instr rd, imm, rs1, and that is how they are constructed in the instruction selector. This fixes the discrepancy. Also fixed some comments along the same lines and fixed page numbers referring to where instructions are described in the Sparc manual. llvm-svn: 6384
* Add dependency to make TableGen rule fire.Brian Gaeke2003-05-281-0/+2
| | | | llvm-svn: 6383
* Fixed an error preventing compilation.Misha Brukman2003-05-272-2/+2
| | | | llvm-svn: 6381
* Added the 'r' and 'i' annotations to instructions as their opcode names haveMisha Brukman2003-05-271-3/+3
| | | | | | changed. llvm-svn: 6380
* Keep track of the current BasicBlock being processed so that a referencingMisha Brukman2003-05-272-2/+4
| | | | | | MachineInstr can later be patched up correctly. llvm-svn: 6378
* Added 'r' and 'i' annotations to instructions as SparcInstr.def has changed.Misha Brukman2003-05-271-19/+22
| | | | llvm-svn: 6377
* Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman2003-05-271-16/+16
| | | | | | | | | Non-obvious change: since I have changed ST and STD to be STF and STDF to (a) closer resemble their name (NOT assembly text) in the Sparc manual, and (b) clearly specify that they they are floating-point opcodes, I made the same changes in this file. llvm-svn: 6376
* Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman2003-05-271-41/+79
| | | | | | | | | | Here I had to make one non-trivial change: add a function to get a version of the opcode that takes an immediate, given an opcode that takes all registers. This is required because sometimes it is not known at construction time which opcode is used because opcodes are passed around between functions. llvm-svn: 6375
* Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman2003-05-273-27/+30
| | | | llvm-svn: 6373
* Added entries for each of the instructions with annotations ('r' or 'i').Misha Brukman2003-05-271-34/+57
| | | | llvm-svn: 6372
* One of the first major changes to make the work of JITting easier: addingMisha Brukman2003-05-271-55/+113
| | | | | | | | | | | | | | | | annotations on instructions to specify which format they are (i.e., do they take 2 registers and 1 immediate or just 3 registers) as that changes their binary representation and hence, code emission. This makes instructions more like how X86 defines them to be. Now, writers of instruction selection must choose the correct opcode based on what instruction type they are building, which they already know. Thus, the JIT doesn't have to do the same work by `discovering' which operands an instruction really has. As this involves lots of small changes to a lot of files in lib/target/Sparc, I'll commit them individually because otherwise the diffs will be unreadable. llvm-svn: 6371
* * Allow passing in an unsigned configuration to allocateSparcTargetMachine()Misha Brukman2003-05-271-10/+35
| | | | | | | | a default value is set in the header file. * Fixed some code layout to make it more consistent with the rest of codebase * Added addPassesToJITCompile() with relevant passes llvm-svn: 6369
* Moved generation of the SparcV9CodeEmitter.inc file higher in the Makefile soMisha Brukman2003-05-271-3/+4
| | | | | | that Makefile.common would see it. llvm-svn: 6367
* Add prototypes to add passes to JIT compilation and code emission.Misha Brukman2003-05-271-8/+17
| | | | | | | | Also, added annotations to how instructions are modified (reg/imm operands). Added prototype for adding register numbers to values pass for interfacing with the target-independent register allocators in the JIT. llvm-svn: 6366
* Broke out class definition from SparcV9CodeEmitter, and added ability to take aMisha Brukman2003-05-272-25/+35
| | | | | | | MachineCodeEmitter to make a pass-through debugger -- output to memory and to std::cerr. llvm-svn: 6363
* SparcV9CodeEmitter.cpp is a part of the Sparc code emitter. The main functionMisha Brukman2003-05-273-0/+94
| | | | | | | | | | | that assembles instructions is generated via TableGen (and hence must be built before building this directory, but that's already the case in the top-level Makefile). Also added is .cvsignore to ignore the generated file `SparcV9CodeEmitter.inc', which is included by SparcV9CodeEmitter.cpp . llvm-svn: 6357
* Added definitions for a bunch of floating-point instructions.Misha Brukman2003-05-271-65/+381
| | | | llvm-svn: 6356
* Added special register class containing (for now) %fsr.Vikram S. Adve2003-05-275-158/+111
| | | | | | | | Fixed spilling of %fcc[0-3] which are part of %fsr. Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. llvm-svn: 6339
* Bug fix: right shift for int divide-by-power-of-2 was incorrect forVikram S. Adve2003-05-251-11/+48
| | | | | | negative values. Need to add one to a negative value before right shift! llvm-svn: 6334
* Bug fix: padding bytes within a structure should go after each field!Vikram S. Adve2003-05-251-5/+5
| | | | llvm-svn: 6333
* Bug fix: sign-extension was not happening for C = -MININT since C == -C!Vikram S. Adve2003-05-251-2/+3
| | | | llvm-svn: 6332
* Add support for compiling varargs functions.Vikram S. Adve2003-05-254-77/+179
| | | | llvm-svn: 6325
* Reword to remove reference to how things worked in the past.Misha Brukman2003-05-241-4/+3
| | | | llvm-svn: 6323
* Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.Misha Brukman2003-05-241-0/+29
| | | | llvm-svn: 6320
* Cleaned up code layout; no functional changes.Misha Brukman2003-05-231-24/+20
| | | | llvm-svn: 6312
* Fixed `volatile' typo.Misha Brukman2003-05-211-1/+1
| | | | llvm-svn: 6266
* Cleaned up code layout, spacing, etc. for readability purposes and to be moreMisha Brukman2003-05-212-307/+281
| | | | | | | | | consistent with the style of LLVM's code base (and itself! it's inconsistent in some places.) No functional changes were made. llvm-svn: 6265
* Cleaned up code layout, spacing, etc. for readability purposes and to be moreMisha Brukman2003-05-211-59/+44
| | | | | | | | | consistent with the style of LLVM's code base (and itself! it's inconsistent in some places.) No functional changes were made. llvm-svn: 6262
* Namespacified `vector' and `cerr' to always use the `std::' namespace.Misha Brukman2003-05-213-88/+90
| | | | | | Eliminated `using' directives. llvm-svn: 6261
* Sparc instruction opcodes now all live under the `V9' namespace.Misha Brukman2003-05-208-568/+569
| | | | llvm-svn: 6249
* Remove wierd printoutChris Lattner2003-05-121-1/+1
| | | | llvm-svn: 6145
* Added the initial version of the TableGen description for the Sparc backend.Misha Brukman2003-05-071-0/+359
| | | | llvm-svn: 6021
* Eliminate use of NonCopyable so that doxygen documentation doesn't linkChris Lattner2003-05-011-3/+4
| | | | | | the Annotation classes with the noncopyable classes for no reason llvm-svn: 5973
* Remove two fields from TargetData which are target specific.Chris Lattner2003-04-261-1/+1
| | | | llvm-svn: 5963
* IntegerRegSize is always 8 for sparcChris Lattner2003-04-262-6/+3
| | | | llvm-svn: 5961
* Fix obvious type-oChris Lattner2003-04-252-3/+3
| | | | llvm-svn: 5932
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