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* [SPARC] Use AtomicExpandPass to expand AtomicRMW instructions.James Y Knight2016-03-291-33/+0
| | | | | | | | | They were previously expanded to CAS loops in a custom isel expansion, but AtomicExpandPass knows how to do that generically. Testing is covered by the existing sparc atomics.ll testcases. llvm-svn: 264771
* Sparc: Add the "alternate address space" load/store instructions.James Y Knight2015-05-181-2/+2
| | | | | | | | | | | | | | | | | | - Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma. - Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa) This does not attempt to hook these instructions up to pointer address spaces in LLVM, although that would probably be a reasonable thing to do in the future. Differential Revision: http://reviews.llvm.org/D8904 llvm-svn: 237581
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-6/+5
| | | | | | | This breaks a test: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870 llvm-svn: 235987
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-5/+6
| | | | | | | | | | | | | | | | | | | | | | | This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235977
* Sparc: disable printing on longer "brX,pt" aliasesTim Northover2014-05-161-2/+2
| | | | | | | This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208965
* [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc ↵Venkatraman Govindaraju2014-03-021-0/+3
| | | | | | backend. llvm-svn: 202670
* [SparcV9] Adds support for branch on integer register instructions (BPr) and ↵Venkatraman Govindaraju2014-03-021-0/+78
| | | | | | conditional moves on integer register (MOVr/FMOVr). llvm-svn: 202628
* [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 ↵Venkatraman Govindaraju2014-03-021-2/+2
| | | | | | | | conditional registers as input. No functionality change. llvm-svn: 202614
* [SparcV9] Add support for parsing branch instructions with prediction.Venkatraman Govindaraju2014-03-011-12/+2
| | | | llvm-svn: 202602
* [Sparc] Add support to disassemble sparc memory instructions.Venkatraman Govindaraju2014-03-011-3/+6
| | | | llvm-svn: 202575
* [Sparc] Emit correct encoding for atomic instructions. Also, add support for ↵Venkatraman Govindaraju2014-02-071-1/+1
| | | | | | parsing CAS instructions to test the CAS encoding. llvm-svn: 200963
* Implement SPARCv9 atomic_swap_64 with a pseudo.Jakob Stoklund Olesen2014-01-301-0/+8
| | | | | | | | The SWAP instruction only exists in a 32-bit variant, but the 64-bit atomic swap can be implemented in terms of CASX, like the other atomic rmw primitives. llvm-svn: 200453
* Implement atomicrmw operations in 32 and 64 bits for SPARCv9.Jakob Stoklund Olesen2014-01-241-0/+25
| | | | | | These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
* [Sparc] Add support for parsing floating point instructions.Venkatraman Govindaraju2014-01-121-18/+18
| | | | llvm-svn: 199033
* [Sparc] Multiclass for loads/stores. No functionality change intended.Venkatraman Govindaraju2014-01-091-24/+4
| | | | llvm-svn: 198893
* [SparcV9] Rename operands in some sparc64 instructions so that TableGen can ↵Venkatraman Govindaraju2014-01-081-9/+9
| | | | | | encode them correctly. llvm-svn: 198740
* [Sparc] Add support for parsing branch instructions and conditional moves.Venkatraman Govindaraju2014-01-081-10/+20
| | | | llvm-svn: 198738
* [Sparc] Add initial implementation of disassembler for sparcVenkatraman Govindaraju2014-01-061-20/+27
| | | | llvm-svn: 198591
* [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.Venkatraman Govindaraju2014-01-041-1/+1
| | | | llvm-svn: 198484
* [Sparc] Handle atomic loads/stores in sparc backend.Venkatraman Govindaraju2014-01-011-0/+26
| | | | llvm-svn: 198286
* [SparcV9] Use separate instruction patterns for 64 bit arithmetic ↵Venkatraman Govindaraju2013-12-291-20/+59
| | | | | | | | instructions instead of reusing 32 bit instruction patterns. This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot. llvm-svn: 198157
* [Sparc]: Implement LEA pattern for sparcv9.Venkatraman Govindaraju2013-11-241-0/+6
| | | | llvm-svn: 195575
* [SparcV9] Handle i64 <-> float conversions in sparcv9 mode.Venkatraman Govindaraju2013-11-031-0/+36
| | | | llvm-svn: 193957
* [SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.Venkatraman Govindaraju2013-11-031-0/+2
| | | | llvm-svn: 193941
* [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.Venkatraman Govindaraju2013-10-061-7/+0
| | | | | | This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes. llvm-svn: 192054
* [Sparc] Clean up branch instructions, so that TableGen can encode branch ↵Venkatraman Govindaraju2013-09-221-3/+3
| | | | | | conditions as well. No functionality change intended. llvm-svn: 191166
* [Sparc] Add support for TLS in sparc.Venkatraman Govindaraju2013-09-221-0/+9
| | | | llvm-svn: 191164
* Remember the anyext patterns.Jakob Stoklund Olesen2013-06-071-0/+2
| | | | llvm-svn: 183589
* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-071-0/+3
| | | | llvm-svn: 183587
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-071-1/+1
| | | | | | I am able to compile/assemble/link/run /bin/echo from FreeBSD. llvm-svn: 183537
* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-071-2/+2
| | | | llvm-svn: 183463
* Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2013-06-031-0/+4
| | | | | | using two instructions (sethi and store). llvm-svn: 183090
* Don't use %g0 to materialize 0 directly.Jakob Stoklund Olesen2013-05-191-4/+0
| | | | | | | | The wired physreg doesn't work on tied operands like on MOVXCC. Add a README note to fix this later. llvm-svn: 182225
* Select i64 values with %icc conditions.Jakob Stoklund Olesen2013-05-191-0/+5
| | | | llvm-svn: 182224
* Add floating point selects on %xcc predicates.Jakob Stoklund Olesen2013-05-191-0/+10
| | | | llvm-svn: 182222
* Implement SPselectfcc for i64 operands.Jakob Stoklund Olesen2013-05-191-1/+6
| | | | | | | Also clean up the arguments to all the MOVCC instructions so the operands always are (true-val, false-val, cond-code). llvm-svn: 182221
* Add 64-bit multiply and divide instructions for SPARC v9.Jakob Stoklund Olesen2013-04-161-0/+39
| | | | llvm-svn: 179582
* Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen2013-04-141-1/+1
| | | | | | Test case by llvm-stress. llvm-svn: 179477
* Implement LowerReturn_64 for SPARC v9.Jakob Stoklund Olesen2013-04-061-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integer return values are sign or zero extended by the callee, and structs up to 32 bytes in size can be returned in registers. The CC_Sparc64 CallingConv definition is shared between LowerFormalArguments_64 and LowerReturn_64. Function arguments and return values are passed in the same registers. The inreg flag is also used for return values. This is required to handle C functions returning structs containing floats and ints: struct ifp { int i; float f; }; struct ifp f(void); LLVM IR: define inreg { i32, float } @f() { ... ret { i32, float } %retval } The ABI requires that %retval.i is returned in the high bits of %i0 while %retval.f goes in %f1. Without the inreg return value attribute, %retval.i would go in %i0 and %retval.f would go in %f3 which is a more efficient way of returning %multiple values, but it is not ABI compliant for returning C structs. llvm-svn: 178966
* Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen2013-04-041-2/+25
| | | | | | | | | | | This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
* Add 64-bit compare + branch for SPARC v9.Jakob Stoklund Olesen2013-04-031-0/+21
| | | | | | | | | | The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. llvm-svn: 178621
* Add 64-bit load and store instructions.Jakob Stoklund Olesen2013-04-021-0/+68
| | | | | | There is only a few new instructions, the rest is handled with patterns. llvm-svn: 178528
* Basic 64-bit ALU operations.Jakob Stoklund Olesen2013-04-021-0/+38
| | | | | | | SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. llvm-svn: 178527
* Materialize 64-bit immediates.Jakob Stoklund Olesen2013-04-021-0/+88
| | | | | | | The last resort pattern produces 6 instructions, and there are still opportunities for materializing some immediates in fewer instructions. llvm-svn: 178526
* Add 64-bit shift instructions.Jakob Stoklund Olesen2013-04-021-0/+47
SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. llvm-svn: 178525
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