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author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-01-09 21:49:18 +0000 |
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committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-01-09 21:49:18 +0000 |
commit | 6ff62cc539afd8da890859ade94ceeede6871c1d (patch) | |
tree | 2f2a292a02c63ea05af164bef7bde09f6c3d54c6 /llvm/lib/Target/Sparc/SparcInstr64Bit.td | |
parent | 98571fd9b7ff744a9139d4861483d70c7de74e37 (diff) | |
download | bcm5719-llvm-6ff62cc539afd8da890859ade94ceeede6871c1d.tar.gz bcm5719-llvm-6ff62cc539afd8da890859ade94ceeede6871c1d.zip |
[Sparc] Multiclass for loads/stores. No functionality change intended.
llvm-svn: 198893
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcInstr64Bit.td')
-rw-r--r-- | llvm/lib/Target/Sparc/SparcInstr64Bit.td | 28 |
1 files changed, 4 insertions, 24 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td index b8dab0582fa..4cb51523d40 100644 --- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -235,14 +235,8 @@ def UDIVXri : F3_2<2, 0b001101, let Predicates = [Is64Bit] in { // 64-bit loads. -def LDXrr : F3_1<3, 0b001011, - (outs I64Regs:$dst), (ins MEMrr:$addr), - "ldx [$addr], $dst", - [(set i64:$dst, (load ADDRrr:$addr))]>; -def LDXri : F3_2<3, 0b001011, - (outs I64Regs:$dst), (ins MEMri:$addr), - "ldx [$addr], $dst", - [(set i64:$dst, (load ADDRri:$addr))]>; +defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>; + let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in def TLS_LDXrr : F3_1<3, 0b001011, (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), @@ -276,24 +270,10 @@ def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; // Sign-extending load of i32 into i64 is a new SPARC v9 instruction. -def LDSWrr : F3_1<3, 0b001000, - (outs I64Regs:$dst), (ins MEMrr:$addr), - "ldsw [$addr], $dst", - [(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>; -def LDSWri : F3_2<3, 0b001000, - (outs I64Regs:$dst), (ins MEMri:$addr), - "ldsw [$addr], $dst", - [(set i64:$dst, (sextloadi32 ADDRri:$addr))]>; +defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>; // 64-bit stores. -def STXrr : F3_1<3, 0b001110, - (outs), (ins MEMrr:$addr, I64Regs:$rd), - "stx $rd, [$addr]", - [(store i64:$rd, ADDRrr:$addr)]>; -def STXri : F3_2<3, 0b001110, - (outs), (ins MEMri:$addr, I64Regs:$rd), - "stx $rd, [$addr]", - [(store i64:$rd, ADDRri:$addr)]>; +defm STX : Store<"stx", 0b001110, store, I64Regs, i64>; // Truncating stores from i64 are identical to the i32 stores. def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>; |