diff options
| author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-02-07 07:34:49 +0000 |
|---|---|---|
| committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-02-07 07:34:49 +0000 |
| commit | ced9226b0f79f85e4e2215b8d2b9746a7262dab1 (patch) | |
| tree | a6f316b372a2f7780ce6355f2e435b7cdfc07889 /llvm/lib/Target/Sparc/SparcInstr64Bit.td | |
| parent | fd07500dd12eeb4bee259c091f0fb7a50d3cd9cb (diff) | |
| download | bcm5719-llvm-ced9226b0f79f85e4e2215b8d2b9746a7262dab1.tar.gz bcm5719-llvm-ced9226b0f79f85e4e2215b8d2b9746a7262dab1.zip | |
[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.
llvm-svn: 200963
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcInstr64Bit.td')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstr64Bit.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td index 9146098a230..a5b48f90340 100644 --- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -415,7 +415,7 @@ def SETHIXi : F2_1<0b100, // ATOMICS. let Predicates = [Is64Bit], Constraints = "$swap = $rd" in { - def CASXrr: F3_1<3, 0b111110, + def CASXrr: F3_1_asi<3, 0b111110, 0b10000000, (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2, I64Regs:$swap), "casx [$rs1], $rs2, $rd", |
