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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [Sparc] Add support for the partial write PSR instructionDaniel Cederman2018-09-271-1/+5
| | | | | | | | | | | | | | | Summary: Partial write %PSR (WRPSR) is a SPARC V8e option that allows WRPSR instructions to only affect the %PSR.ET field. It is supported by the GR740 and GR716. Reviewers: jyknight, venkatra Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48644 llvm-svn: 343202
* [Sparc] Add support for the cycle counter available in GR740Daniel Cederman2018-08-271-1/+1
| | | | | | | | | | | | | | | | | Summary: The GR740 provides an up cycle counter in the registers ASR22 and ASR23. As these registers can not be read together atomically we only use the value of ASR23 for llvm.readcyclecounter(). The ASR23 register holds the 32 LSBs of the up-counter. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: jfb, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48638 llvm-svn: 340733
* Revert "[Sparc] Add support for the cycle counter available in GR740"Daniel Cederman2018-08-131-1/+1
| | | | | | | It breaks when using EXPENSIVE_CHECKS with the error message "Bad machine code: Using an undefined physical register". llvm-svn: 339570
* [Sparc] Add support for the cycle counter available in GR740Daniel Cederman2018-08-131-1/+1
| | | | | | | | | | | | | | | | | | Summary: The GR740 provides an up cycle counter in the registers ASR22 and ASR23. As these registers can not be read together atomically we only use the value of ASR23 for llvm.readcyclecounter(). The ASR23 register holds the 32 LSBs of the up-counter. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D48638 llvm-svn: 339551
* Revert "This pass, fixing an erratum in some LEON 2 processors..."Daniel Cederman2018-04-201-1/+1
| | | | | | | | | | | | | | | | | | | | | Summary: Reading Atmel's AT697E errata document this does not seem like a valid workaround. While the text only mentions SDIV, it says that the ICC flags can be wrong, and those are only generated by SDIVcc. Verification on hardware shows that simply replacing SDIV with SDIVcc does not avoid the bug with negative operands. This reverts r283727. Reviewers: lero_chris, jyknight Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45813 llvm-svn: 330397
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* Add support for Myriad ma2x8x series of CPUsWalter Lee2017-10-021-0/+9
| | | | | | | | | | | | Summary: Also add support for some older Myriad CPUs that were missing. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37552 llvm-svn: 314705
* [SPARC] Clean up the support for disabling fsmuld and fmuls instructions.James Y Knight2017-07-201-5/+12
| | | | | | | | | | | | | | | | | Summary: Also enable no-fsmuld for sparcv7 (which doesn't have the instruction). The previous code which used a post-processing pass to do this was unnecessary; disabling the instruction is entirely sufficient. Reviewers: jacob_hansen, ekedaigle Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D35576 llvm-svn: 308661
* [Sparc] Added software multiplication/division featureJames Y Knight2017-07-181-1/+5
| | | | | | | | | | | Added a feature to the Sparc back-end that replaces the integer multiply and divide instructions with calls to .mul/.sdiv/.udiv. This is a step towards having full v7 support. Patch by: Eric Kedaigle Differential Revision: https://reviews.llvm.org/D35500 llvm-svn: 308343
* This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV ↵Chris Dewhurst2016-10-101-1/+1
| | | | | | | | instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included. Differential Review: https://reviews.llvm.org/D24660 llvm-svn: 283727
* [Myriad]: set LeonCASA processor featureDouglas Katzman2016-09-131-6/+6
| | | | llvm-svn: 281359
* [Myriad]: add missing 'mcpu' valuesDouglas Katzman2016-08-291-0/+3
| | | | | | Should have been done with r276646. llvm-svn: 279996
* Revert "[Sparc] Leon errata fix passes."James Y Knight2016-08-121-75/+70
| | | | | | | | | | | ...and the two followup commits: Revert "[Sparc][Leon] Missed resetting option flags from check-in 278489." Revert "[Sparc][Leon] Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor." This reverts commit r274856, r278489, and r278492. llvm-svn: 278511
* [Sparc][Leon] Errata fixes for various errata in different versions of the ↵Chris Dewhurst2016-08-121-2/+3
| | | | | | | | | | | | Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. These changes update older versions of these errata fixes with improvements to code and unit tests. Differential Revision: https://reviews.llvm.org/D21960 llvm-svn: 278489
* [Sparc] Leon errata fix passes.Chris Dewhurst2016-07-081-70/+74
| | | | | | | | | | | | Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 llvm-svn: 274856
* [SPARC] Fixes for hardware errata on LEON processor.Chris Dewhurst2016-06-191-1/+1
| | | | | | | | | | Passes to fix three hardware errata that appear on some LEON processor variants. The instructions FSMULD, FMULS and FDIVS do not work as expected on some LEON processors. This change allows those instructions to be substituted for alternatives instruction sequences that are known to work. These passes only run when selected individually, or as part of a processor defintion. They are not included in general SPARC processor compilations for non-LEON processors or for those LEON processors that do not have these hardware errata. llvm-svn: 273108
* [Sparc][LEON] LEON Erratum fix. Insert NOP after LD or LDF instruction.Chris Dewhurst2016-05-231-4/+4
| | | | | | | | | | Due to an erratum in some versions of LEON, we must insert a NOP after any LD or LDF instruction to ensure the processor has time to load the value correctly before using it. This pass will implement that erratum fix. The code will have no effect for other Sparc, but non-LEON processors. Differential Review: http://reviews.llvm.org/D20353 llvm-svn: 270417
* [Sparc] Add Soft Float supportChris Dewhurst2016-05-181-0/+3
| | | | | | | | | | This change adds support for software floating point operations for Sparc targets. This is the first in a set of patches to enable software floating point on Sparc. The next patch will enable the option to be used with Clang. Differential Revision: http://reviews.llvm.org/D19265 llvm-svn: 269892
* [Sparc][LEON] Add LEON-specific CASA instruction.Chris Dewhurst2016-05-161-7/+7
| | | | | | Differental Revision: http://reviews.llvm.org/D20098 llvm-svn: 269644
* [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargetsChris Dewhurst2016-05-091-5/+8
| | | | | | | | | | | | This change adds SMAC (signed multiply-accumulate) and UMAC (unsigned multiply-accumulate) for LEON subtargets of the Sparc processor. The new files LeonFeatures.td and leon-instructions.ll will both be expanded in future, so I want to leave them separate as small files for this review, to be expanded in future check-ins. Note: The functions are provided only for inline-assembly provision. No DAG selection is provided. Differential Revision: http://reviews.llvm.org/D19911 llvm-svn: 268908
* [Sparc] This provides support for itineraries on Sparc.Chris Dewhurst2016-04-221-0/+41
| | | | | | | | | | | | Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future. The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this. As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary. Phabricator Review: http://reviews.llvm.org/D19359 llvm-svn: 267121
* Myriad: Add new sparc CPU kinds.Douglas Katzman2016-03-151-0/+3
| | | | llvm-svn: 263557
* [SparcInstPrinter] Use the subtarget that is passed to the print functionAkira Hatanaka2015-03-281-0/+7
| | | | | | | | | | | instead of the one passed to the constructor. Unfortunately, I don't have a test case for this change. In order to test my change, I will have to run the code after line 90 in printSparcAliasInstr. I couldn't make that happen because printAliasInstr would always handle the printing of fcmp instructions that the code after line 90 is supposed to handle. llvm-svn: 233471
* [Sparc] Add VIS instructions to sparc backend.Venkatraman Govindaraju2014-03-021-6/+17
| | | | llvm-svn: 202660
* Only generate the popc instruction for SPARC CPUs that implement it.Jakob Stoklund Olesen2014-01-261-3/+6
| | | | | | | The popc instruction is defined in the SPARCv9 instruction set architecture, but it was emulated on CPUs older than Niagara 2. llvm-svn: 200131
* [Sparc] Add missing processor types: v7 and niagaraVenkatraman Govindaraju2014-01-111-1/+5
| | | | llvm-svn: 199024
* [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.Venkatraman Govindaraju2014-01-041-0/+5
| | | | llvm-svn: 198484
* [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.Venkatraman Govindaraju2013-12-261-7/+0
| | | | llvm-svn: 198030
* Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola2013-12-021-0/+7
| | | | llvm-svn: 196065
* [Sparc] Add long double (f128) instructions to sparc backend. Venkatraman Govindaraju2013-08-251-0/+4
| | | | llvm-svn: 189198
* Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,Venkatraman Govindaraju2013-06-041-1/+1
| | | | llvm-svn: 183243
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-3/+3
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* fix emacs language spec's, patch by Edmund Grimley-Evans!Chris Lattner2010-08-171-1/+1
| | | | llvm-svn: 111241
* Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen2010-04-051-5/+1
| | | | | | | | | | | | | | | | | | | When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
* Move target independent td files from lib/Target/ to include/llvm/Target so ↵Evan Cheng2008-11-241-1/+1
| | | | | | they can be distributed along with the header files. llvm-svn: 59953
* Start moving sparc to use SparcCallingConv.td, switching overChris Lattner2008-03-171-6/+2
| | | | | | | return lowering first. This fixes a bug where the top and bottom of i64 values were returned in the wrong registers before. llvm-svn: 48443
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-3/+0
| | | | llvm-svn: 28378
* Remove PointerType from class TargetEvan Cheng2006-05-171-3/+0
| | | | llvm-svn: 28368
* Rename SPARC V8 target to be the LLVM SPARC target.Chris Lattner2006-02-051-0/+86
llvm-svn: 25985
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