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authorVenkatraman Govindaraju <venkatra@cs.wisc.edu>2014-01-04 11:30:13 +0000
committerVenkatraman Govindaraju <venkatra@cs.wisc.edu>2014-01-04 11:30:13 +0000
commitc2dee7dc742f518fdd57d3c357cb28b2d2ffe79f (patch)
tree84d889bc74e8cd104dfcc47732e96d03d7fb5c76 /llvm/lib/Target/Sparc/Sparc.td
parentacb42aefd766f2614f8e6e34f5d41b7815e274bd (diff)
downloadbcm5719-llvm-c2dee7dc742f518fdd57d3c357cb28b2d2ffe79f.tar.gz
bcm5719-llvm-c2dee7dc742f518fdd57d3c357cb28b2d2ffe79f.zip
[Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.
llvm-svn: 198484
Diffstat (limited to 'llvm/lib/Target/Sparc/Sparc.td')
-rw-r--r--llvm/lib/Target/Sparc/Sparc.td5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 0df48f60e8f..2cace099b14 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -44,6 +44,10 @@ include "SparcInstrInfo.td"
def SparcInstrInfo : InstrInfo;
+def SparcAsmParser : AsmParser {
+ bit ShouldEmitMatchRegisterName = 0;
+}
+
//===----------------------------------------------------------------------===//
// SPARC processors supported.
//===----------------------------------------------------------------------===//
@@ -73,4 +77,5 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
def Sparc : Target {
// Pull in Instruction Info:
let InstructionSet = SparcInstrInfo;
+ let AssemblyParsers = [SparcAsmParser];
}
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