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* Sparc: Add the "alternate address space" load/store instructions.James Y Knight2015-05-181-0/+11
| | | | | | | | | | | | | | | | | | - Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma. - Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa) This does not attempt to hook these instructions up to pointer address spaces in LLVM, although that would probably be a reasonable thing to do in the future. Differential Revision: http://reviews.llvm.org/D8904 llvm-svn: 237581
* Add support for the Sparc implementation-defined "ASR" registers.James Y Knight2015-05-181-0/+19
| | | | | | | | | | (Note that register "Y" is essentially just ASR0). Also added some test cases for divide and multiply, which had none before. Differential Revision: http://reviews.llvm.org/D8670 llvm-svn: 237580
* Remove 3 includes from MCInstrDesc.h and explicitly include them where neededPete Cooper2015-05-151-0/+1
| | | | llvm-svn: 237481
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-12/+12
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* [Sparc] Really add sparcel architecture support.Douglas Katzman2015-04-291-15/+18
| | | | | | | | Mostly copy-and-paste from Sparc v8 architecture. Differential Revision: http://reviews.llvm.org/D8741 llvm-svn: 236146
* Pass an ArrayRef to MCDisassembler::getInstruction.Rafael Espindola2014-11-121-11/+7
| | | | | | | | | | | | With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t> instead of a MemoryObject. Even on X86 there is a maximum size an instruction can have. Given that, it seems way simpler and more efficient to just pass an ArrayRef to the disassembler instead of a MemoryObject and have it do a virtual call every time it wants some extra bytes. llvm-svn: 221751
* Misc style fixes. NFC.Rafael Espindola2014-11-101-35/+22
| | | | | | | | | | | | | This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-6/+6
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Sparc edition llvm-svn: 207502
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-151-8/+5
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* [Sparc] Add support for decoding 'swap' instruction.Venkatraman Govindaraju2014-03-091-0/+36
| | | | llvm-svn: 203424
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-021-0/+30
| | | | llvm-svn: 202666
* [Sparc] Add support for decoding jmpl/retl/ret instruction.Venkatraman Govindaraju2014-03-021-0/+36
| | | | llvm-svn: 202663
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-021-0/+13
| | | | llvm-svn: 202610
* [Sparc] Add support to decode negative simm13 operands in the sparc ↵Venkatraman Govindaraju2014-03-011-0/+9
| | | | | | disassembler. llvm-svn: 202578
* [Sparc] Add support for decoding call instructions in the sparc disassembler.Venkatraman Govindaraju2014-03-011-0/+21
| | | | llvm-svn: 202577
* [Sparc] Add support to disassemble sparc memory instructions.Venkatraman Govindaraju2014-03-011-0/+110
| | | | llvm-svn: 202575
* [Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner.Venkatraman Govindaraju2014-01-121-9/+9
| | | | llvm-svn: 199031
* [Sparc] Explicitly cast -1 to unsigned to fix buildbot errors.Venkatraman Govindaraju2014-01-061-8/+8
| | | | llvm-svn: 198592
* [Sparc] Add initial implementation of disassembler for sparcVenkatraman Govindaraju2014-01-061-0/+228
llvm-svn: 198591
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