diff options
author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-09 23:32:07 +0000 |
---|---|---|
committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2014-03-09 23:32:07 +0000 |
commit | f703132b09a2b5a53461f2b220e2f8e548d46c47 (patch) | |
tree | aa0cfd83667e85f94d1f0fc7475a18c91bf4481a /llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp | |
parent | a2790b106d2e83e29891e80f2ece172c8c3a305c (diff) | |
download | bcm5719-llvm-f703132b09a2b5a53461f2b220e2f8e548d46c47.tar.gz bcm5719-llvm-f703132b09a2b5a53461f2b220e2f8e548d46c47.zip |
[Sparc] Add support for decoding 'swap' instruction.
llvm-svn: 203424
Diffstat (limited to 'llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp')
-rw-r--r-- | llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index df2d3798a24..5cd99d6bfe0 100644 --- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -211,6 +211,8 @@ static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, + const void *Decoder); #include "SparcGenDisassemblerTables.inc" @@ -445,3 +447,37 @@ static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, } return MCDisassembler::Success; } + +static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, + const void *Decoder) { + + unsigned rd = fieldFromInstruction(insn, 25, 5); + unsigned rs1 = fieldFromInstruction(insn, 14, 5); + unsigned isImm = fieldFromInstruction(insn, 13, 1); + unsigned rs2 = 0; + unsigned simm13 = 0; + if (isImm) + simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); + else + rs2 = fieldFromInstruction(insn, 0, 5); + + // Decode RD. + DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + + // Decode RS1. + status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + + // Decode RS1 | SIMM13. + if (isImm) + MI.addOperand(MCOperand::CreateImm(simm13)); + else { + status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); + if (status != MCDisassembler::Success) + return status; + } + return MCDisassembler::Success; +} |