| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Fix 64-bit data layout mismatch between backend and target description | Mandeep Singh Grang | 2017-11-16 | 1 | -1/+1 |
| * | [RISCV] Initial codegen support for ALU operations | Alex Bradbury | 2017-10-19 | 1 | -2/+24 |
| * | Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine" | Matthias Braun | 2017-10-12 | 1 | -3/+3 |
| * | TargetMachine: Merge TargetMachine and LLVMTargetMachine | Matthias Braun | 2017-10-12 | 1 | -3/+3 |
| * | Delete Default and JITDefault code models | Rafael Espindola | 2017-08-03 | 1 | -3/+10 |
| * | Sort the remaining #include lines in include/... and lib/.... | Chandler Carruth | 2017-06-06 | 1 | -1/+1 |
| * | TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFC | Matthias Braun | 2017-05-30 | 1 | -1/+1 |
| * | [RISCV] Fix RV32 datalayout string and ensure initAsmInfo is called | Alex Bradbury | 2017-02-14 | 1 | -2/+4 |
| * | [RISCV] Add stub backend | Alex Bradbury | 2016-11-01 | 1 | -0/+58 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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