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author | Alex Bradbury <asb@lowrisc.org> | 2017-02-14 05:20:20 +0000 |
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committer | Alex Bradbury <asb@lowrisc.org> | 2017-02-14 05:20:20 +0000 |
commit | e4f731b81308274ab2da8f0fed88420905760d42 (patch) | |
tree | 1c40dac3608c85b83f1d71f83d5a68dfd60e29da /llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | |
parent | 6be16fbfb8107dcc72e9fd2c15a6350013dfc162 (diff) | |
download | bcm5719-llvm-e4f731b81308274ab2da8f0fed88420905760d42.tar.gz bcm5719-llvm-e4f731b81308274ab2da8f0fed88420905760d42.zip |
[RISCV] Fix RV32 datalayout string and ensure initAsmInfo is called
llvm-svn: 295028
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVTargetMachine.cpp')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index afbbe004186..a20331cd0a3 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -32,7 +32,7 @@ static std::string computeDataLayout(const Triple &TT) { return "e-m:e-i64:64-n32:64-S128"; } else { assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); - return "e-m:e-i64:64-n32-S128"; + return "e-m:e-p:32:32-i64:64-n32-S128"; } } @@ -51,7 +51,9 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, CodeGenOpt::Level OL) : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM), CM, OL), - TLOF(make_unique<TargetLoweringObjectFileELF>()) {} + TLOF(make_unique<TargetLoweringObjectFileELF>()) { + initAsmInfo(); +} TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { return new TargetPassConfig(this, PM); |