| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Implementation of asm-goto support in LLVM | Craig Topper | 2019-02-08 | 1 | -1/+2 |
| * | Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI | Ana Pazos | 2019-01-25 | 1 | -0/+13 |
| * | Revert "[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI" | Ana Pazos | 2019-01-24 | 1 | -13/+0 |
| * | [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI | Ana Pazos | 2019-01-24 | 1 | -0/+13 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [RISCV] Remove overzealous is64Bit checks | Alex Bradbury | 2018-10-04 | 1 | -2/+1 |
| * | [RISCV] Add support for _interrupt attribute | Ana Pazos | 2018-07-26 | 1 | -2/+4 |
| * | [RISCV] Lower the tail pseudoinstruction | Mandeep Singh Grang | 2018-05-23 | 1 | -0/+1 |
| * | [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot | Alex Bradbury | 2018-04-26 | 1 | -0/+49 |
| * | [RISCV] Expand function call to "call" pseudoinstruction | Shiva Chen | 2018-04-25 | 1 | -0/+2 |
| * | Revert "[RISCV] implement li pseudo instruction" | Alex Bradbury | 2018-04-18 | 1 | -2/+11 |
| * | [RISCV] implement li pseudo instruction | Alex Bradbury | 2018-04-17 | 1 | -11/+2 |
| * | [RISCV] Codegen support for RV32D floating point comparison operations | Alex Bradbury | 2018-04-12 | 1 | -7/+11 |
| * | [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ... | Alex Bradbury | 2018-04-12 | 1 | -0/+4 |
| * | [RISCV] Codegen support for RV32F floating point comparison operations | Alex Bradbury | 2018-03-21 | 1 | -10/+31 |
| * | [RISCV] Implement support for the BranchRelaxation pass | Alex Bradbury | 2018-01-10 | 1 | -5/+110 |
| * | [RISCV] Implement branch analysis | Alex Bradbury | 2018-01-10 | 1 | -0/+166 |
| * | [RISCV] Support stack frames and offsets up to 32-bits | Alex Bradbury | 2018-01-10 | 1 | -0/+20 |
| * | [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/lo... | Alex Bradbury | 2017-12-07 | 1 | -2/+2 |
| * | [RISCV] Initial support for function calls | Alex Bradbury | 2017-11-08 | 1 | -1/+2 |
| * | [RISCV] Codegen for conditional branches | Alex Bradbury | 2017-11-08 | 1 | -0/+33 |
| * | [RISCV] Codegen support for memory operations | Alex Bradbury | 2017-11-08 | 1 | -0/+12 |
| * | [RISCV] Initial codegen support for ALU operations | Alex Bradbury | 2017-10-19 | 1 | -0/+31 |
