| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Implement support for the BranchRelaxation pass | Alex Bradbury | 2018-01-10 | 1 | -5/+110 |
| * | [RISCV] Implement branch analysis | Alex Bradbury | 2018-01-10 | 1 | -0/+166 |
| * | [RISCV] Support stack frames and offsets up to 32-bits | Alex Bradbury | 2018-01-10 | 1 | -0/+20 |
| * | [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/lo... | Alex Bradbury | 2017-12-07 | 1 | -2/+2 |
| * | [RISCV] Initial support for function calls | Alex Bradbury | 2017-11-08 | 1 | -1/+2 |
| * | [RISCV] Codegen for conditional branches | Alex Bradbury | 2017-11-08 | 1 | -0/+33 |
| * | [RISCV] Codegen support for memory operations | Alex Bradbury | 2017-11-08 | 1 | -0/+12 |
| * | [RISCV] Initial codegen support for ALU operations | Alex Bradbury | 2017-10-19 | 1 | -0/+31 |

