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path: root/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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* [RISCV] Implement support for the BranchRelaxation passAlex Bradbury2018-01-101-5/+110
* [RISCV] Implement branch analysisAlex Bradbury2018-01-101-0/+166
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-101-0/+20
* [RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/lo...Alex Bradbury2017-12-071-2/+2
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-1/+2
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-0/+33
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-081-0/+12
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+31
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