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path: root/llvm/lib/Target/RISCV/RISCVInstrFormats.td
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Scheduler description for the Rocket coreKai Wang2020-02-031-1/+2
* [RISCV] Implement pseudo instructions for load/store from a symbol address.Kito Cheng2019-02-201-0/+29
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV][NFC] Define and use the new CA instruction formatAlex Bradbury2018-11-161-4/+5
* [RISCV] AsmParser support for the li pseudo instructionAlex Bradbury2018-06-071-2/+2
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-2/+2
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-2/+2
* [RISCV] MC layer support for load/store instructions of the C (compressed) ex...Alex Bradbury2017-12-071-4/+12
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-071-0/+17
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-6/+41
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-091-0/+18
* [RISCV] Prepare for the use of variable-sized register classesAlex Bradbury2017-10-191-34/+66
* [RISCV] Add common fixups and relocationsAlex Bradbury2017-09-281-10/+27
* [RISCV] Add support for disassemblyAlex Bradbury2017-09-171-0/+5
* [RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstrAlex Bradbury2017-02-141-1/+2
* [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.tdAlex Bradbury2016-11-011-0/+152
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