summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Define getSetCCResultType for setting vector setCC typeShiva Chen2018-02-021-0/+7
* [RISCV] Codegen support for the standard RV32M instruction set extensionAlex Bradbury2018-01-181-8/+10
* [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsicsAlex Bradbury2018-01-101-0/+57
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-101-0/+18
* [RISCV] Support for varargsAlex Bradbury2018-01-101-20/+125
* [RISCV][NFC] Resolve unused variable warning in RISCVISelLoweringAlex Bradbury2018-01-021-2/+1
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-111-33/+361
* [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestoreAlex Bradbury2017-12-111-0/+5
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-211-15/+91
* [RISCV] Implement lowering of ISD::SELECTAlex Bradbury2017-11-211-0/+152
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-0/+132
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-0/+1
* [RISCV] Codegen support for memory operations on global addressesAlex Bradbury2017-11-081-0/+25
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-081-0/+3
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+170
OpenPOWER on IntegriCloud