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| author | Alex Bradbury <asb@lowrisc.org> | 2017-11-08 12:20:01 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-11-08 12:20:01 +0000 |
| commit | cfa6291bb1ae1d1d66467b662169af9453b7d846 (patch) | |
| tree | f270e27c3ec2e0e8e02d59aa0af49a8d0c0e9647 /llvm/lib/Target/RISCV/RISCVISelLowering.cpp | |
| parent | 0f0e1b54f07bb63ca8da28399028e2d5387ce500 (diff) | |
| download | bcm5719-llvm-cfa6291bb1ae1d1d66467b662169af9453b7d846.tar.gz bcm5719-llvm-cfa6291bb1ae1d1d66467b662169af9453b7d846.zip | |
[RISCV] Codegen support for memory operations
This required the implementation of RISCVTargetInstrInfo::copyPhysReg. Support
for lowering global addresses follow in the next patch.
Differential Revision: https://reviews.llvm.org/D29934
llvm-svn: 317685
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index d76170b7b78..70e33a25941 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -49,6 +49,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setStackPointerRegisterToSaveRestore(RISCV::X2); + for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) + setLoadExtAction(N, XLenVT, MVT::i1, Promote); + // TODO: add all necessary setOperationAction calls. setBooleanContents(ZeroOrOneBooleanContent); |
