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path: root/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Use addi rather than add x0Sam Elliott2019-11-141-3/+3
* [RISCV] Convert registers from unsigned to RegisterLuis Marques2019-08-161-5/+5
* [risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-121-22/+22
* [RISCV] Add lowering of global TLS addressesLewis Revill2019-06-191-0/+28
* [RISCV] Add lowering of addressing sequences for PICLewis Revill2019-06-111-4/+39
* [RISCV] Generate address sequences suitable for mcmodel=mediumAlex Bradbury2019-04-011-0/+45
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Add codegen support for RV64AAlex Bradbury2019-01-171-14/+67
* [RISCV] Implement codegen for cmpxchg on RV32IAAlex Bradbury2018-11-291-0/+104
* [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32AAlex Bradbury2018-09-191-0/+452
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