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path: root/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
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* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-251-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To do this: 1. Add PseudoCALLIndirct to match indirect function call. 2. Add PseudoCALL to support parsing and print pseudo `call` in assembly 3. Expand PseudoCALL to the following form with R_RISCV_CALL relocation type while encoding: auipc ra, func jalr ra, ra, 0 If we expand PseudoCALL before emitting assembly, we will see auipc and jalr pair when compile with -S. It's hard for assembly parser to parsing this pair and identify it's semantic is function call and then insert R_RISCV_CALL relocation type. Although we could insert R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I relocation types instead of R_RISCV_CALL. Due to RISCV relocation design, auipc and jalr pair only can relax to jal with R_RISCV_CALL + R_RISCV_RELAX relocation types. We expand PseudoCALL as late as encoding(RISCVMCCodeEmitter) instead of before emitting assembly(RISCVAsmPrinter) because we want to preserve call pseudoinstruction in assembly code. It's more readable and assembly parser could identify call assembly and insert R_RISCV_CALL relocation type. Differential Revision: https://reviews.llvm.org/D45859 llvm-svn: 330826
* [RISCV] Add support for %pcrel_lo.Ahmed Charles2018-02-061-0/+4
| | | | llvm-svn: 324303
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-071-0/+4
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40002 Patch by Shiva Chen. llvm-svn: 320038
* [RISCV] Bugfix createRISCVELFObjectWriterAlex Bradbury2017-10-181-1/+1
| | | | | | | r315275 set the IsLittleEndian parameter incorrectly. This patch corrects this, and adds a test to ensure such mistakes will be caught in the future. llvm-svn: 316091
* [RISCV] Fix build after r315327Alex Bradbury2017-10-111-2/+4
| | | | | | | Differential Revision: https://reviews.llvm.org/D38779 Patch by Chih-Mao Chen. llvm-svn: 315455
* [RISCV] Fix build after r315254Alex Bradbury2017-10-101-2/+3
| | | | | | | createELFObjectWriter now takes a std::unique_ptr<MCELFObjectTargetWriter> rather than a MCELFObjectTargetWriter*. llvm-svn: 315275
* [RISCV] Add common fixups and relocationsAlex Bradbury2017-09-281-1/+22
| | | | | | | | | | | | | %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
* [RISCV] Fix two abuses of llvm_unreachableAlex Bradbury2017-08-201-1/+1
| | | | | | Replace with report_fatal_error. llvm-svn: 311276
* [RISCV] Set HasRelocationAddend for RISCVELFObjectWriterAlex Bradbury2017-08-201-1/+1
| | | | llvm-svn: 311275
* Removing a switch statement that contains a default label, but no case ↵Aaron Ballman2016-11-021-5/+1
| | | | | | labels. Silences an MSVC warning; NFC. llvm-svn: 285806
* [RISCV] Add bare-bones RISC-V MCTargetDescAlex Bradbury2016-11-011-0/+51
This is enough to compile and link but doesn't yet do anything particularly useful. Once an ASM parser and printer are added in the next two patches, the whole thing can be usefully tested. Differential Revision: https://reviews.llvm.org/D23562 llvm-svn: 285770
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