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* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-015-9/+19
| | | | llvm-svn: 191788
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-302-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-281-1/+1
| | | | llvm-svn: 191611
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-283-44/+40
| | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 191603
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-281-4/+12
| | | | | | | | | | | SelectionDAG will now attempt to inverse an illegal conditon in order to find a legal one and if that doesn't work, it will attempt to swap the operands using the inverted condition. There are no new test cases for this, but a nubmer of the existing R600 tests hit this path. llvm-svn: 191602
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-282-76/+58
| | | | | | | | | | | | This is useful for targets like R600, which only support GT, GE, NE, and EQ condition codes as it removes the need to handle unsupported condition codes in target specific code. There are no tests with this commit, but R600 has been updated to take advantage of this new feature, so its existing selectcc tests are now testing the swapped operands path. llvm-svn: 191601
* MC: Remove vestigial PCSymbol field from AsmInfoDavid Majnemer2013-09-251-1/+0
| | | | llvm-svn: 191362
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-0/+1
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
* Allow subtarget selection of the default MachineScheduler and document the ↵Andrew Trick2013-09-202-8/+14
| | | | | | | | | | | interface. The global registry is used to allow command line override of the scheduler selection, but does not work well as the normal selection API. For example, the same LLVM process should be able to target multiple targets or subtargets. llvm-svn: 191071
* R600: Move clamp handling code to R600IselLowering.cppVincent Lejeune2013-09-122-33/+17
| | | | llvm-svn: 190645
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-122-109/+59
| | | | llvm-svn: 190644
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-123-245/+197
| | | | | | | This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643
* R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedbackTom Stellard2013-09-127-5/+113
| | | | | | | | | | | | | For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist. The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take a resource descriptor might be nicer. The maximum number of input SGPRs is bumped to 17. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190575
* R600: Don't use trans slot for instructions that read LDS source registersTom Stellard2013-09-125-1/+34
| | | | | | | | | | | | | | | | This fixes some regressions in the piglit local memory store tests introduced by recent commits which made the scheduler aware of the trans slot. It's not possible to test this using lit, because there is no way to determine from the assembly dumps whether or not an instruction is in the trans slot. Even if this were possible, the test would be highly sensitive to changes in the scheduler and might generate confusing false negatives. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 190574
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-3/+5
| | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> llvm-svn: 190290
* R600: Add support for LDS atomic subtractAaron Watry2013-09-063-0/+13
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190200
* R600: Coding styleTom Stellard2013-09-051-6/+4
| | | | llvm-svn: 190110
* R600: Fix i64 to i32 trunc on SIMatt Arsenault2013-09-051-0/+1
| | | | llvm-svn: 190091
* R600: Add support for local memory atomic addTom Stellard2013-09-057-14/+78
| | | | llvm-svn: 190080
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-052-15/+6
| | | | llvm-svn: 190079
* R600: Fix incorrect LDS size calculationTom Stellard2013-09-052-4/+14
| | | | | | | GlobalAdderss nodes that appeared in more than one basic block were being counted twice. llvm-svn: 190078
* R600/SI: Don't emit S_WQM_B64 instruction for compute shadersTom Stellard2013-09-051-1/+2
| | | | llvm-svn: 190077
* R600: Fix segfault in R600TextureIntrinsicReplacerTom Stellard2013-09-051-0/+3
| | | | | | | | | | This pass was segfaulting when it ran into a non-intrinsic function call. Function calls are not supported, so now instead of segfaulting, we will get an assertion failure with a nice error message. I'm not sure how to test this using lit. llvm-svn: 190076
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-041-0/+2
| | | | llvm-svn: 189981
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-044-19/+60
| | | | llvm-svn: 189980
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-044-23/+19
| | | | llvm-svn: 189979
* Add llvm namespace to llvm::next.Michael Gottesman2013-09-041-2/+2
| | | | llvm-svn: 189912
* Use llvm::next() instead of incrementing begin iterators of std::vector.Michael Gottesman2013-09-041-2/+2
| | | | | | | | | | Iterator of std::vector may be implemented as a raw pointer. In this case begin iterators are rvalues and cannot be incremented. For example, this is the case with STDCXX implementation of vector. Patch by Konstantin Tokarev <annulen@yandex.ru>. llvm-svn: 189911
* Mark an unreachable code path with llvm_unreachable. Pacifies GCC.Benjamin Kramer2013-08-311-0/+1
| | | | llvm-svn: 189726
* R600: Add support for vector local memory loadsTom Stellard2013-08-264-0/+50
| | | | llvm-svn: 189226
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-264-16/+59
| | | | llvm-svn: 189225
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-268-15/+60
| | | | llvm-svn: 189223
* R600: Add support for v4i32 and v2i32 local storesTom Stellard2013-08-263-59/+107
| | | | llvm-svn: 189222
* SelectionDAG: Use correct pointer size when lowering function arguments v2Tom Stellard2013-08-264-7/+12
| | | | | | | | | | | | | | | | This adds minimal support to the SelectionDAG for handling address spaces with different pointer sizes. The SelectionDAG should now correctly lower pointer function arguments to the correct size as well as generate the correct code when lowering getelementptr. This patch also updates the R600 DataLayout to use 32-bit pointers for the local address space. v2: - Add more helper functions to TargetLoweringBase - Use CHECK-LABEL for tests llvm-svn: 189221
* R600/SI: Fix another case of illegal VGPR to SGPR copyTom Stellard2013-08-221-1/+1
| | | | | | | | This fixes a crash in Unigine Tropics. https://bugs.freedesktop.org/show_bug.cgi?id=68389 llvm-svn: 189057
* R600: Remove unnecessary castsTom Stellard2013-08-211-8/+6
| | | | | | Spotted by Bill Wendling. llvm-svn: 188942
* Remove unused stdio.h includesDmitri Gribenko2013-08-183-3/+0
| | | | llvm-svn: 188626
* R600: Fix possible use of an uninitialized variableTom Stellard2013-08-171-0/+1
| | | | | | Spotted by Nick Lewycky! llvm-svn: 188599
* R600: Expand vector FRINT opsTom Stellard2013-08-161-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
* R600: Expand vector FFLOOR opsTom Stellard2013-08-161-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188597
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-162-13/+18
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188596
* R600/SI: Add pattern for xor of i1Michel Danzer2013-08-161-1/+3
| | | | | | | Fixes two recent piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188559
* R600/SI: Fix broken encoding of DS_WRITE_B32Michel Danzer2013-08-165-9/+23
| | | | | | | | | | | | | | The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused it to corrupt the encoding of that by clobbering the first operand with the second one. Undo that damage and only apply the SMRD logic to that. Fixes some derivates related piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188558
* R600: Allocate memoperand in the MachienFunction so it doesn't leak.Benjamin Kramer2013-08-161-3/+4
| | | | llvm-svn: 188555
* Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"Tom Stellard2013-08-163-8/+10
| | | | | | | This reverts commit a6a39ced095c2f453624ce62c4aead25db41a18f. This is the wrong version of this fix. llvm-svn: 188523
* R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructionsTom Stellard2013-08-163-10/+8
| | | | | | | | | The SIInsertWaits pass was overwriting the first operand (gds bit) of DS_WRITE_B32 with the second operand (value to write). This meant that any time the value to write was stored in an odd number VGPR, the gds bit would be set causing the instruction to write to GDS instead of LDS. llvm-svn: 188522
* R600: Add support for global vector loads with element types less than 32-bitsTom Stellard2013-08-161-0/+13
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188521
* R600: Add support for global vector stores with elements less than 32-bitsTom Stellard2013-08-163-1/+72
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188520
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-168-27/+106
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188519
* R600: Add support for v4i32 stores on CaymanTom Stellard2013-08-161-0/+1
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188518
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