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* R600/SI: Move splitting 64-bit immediates to separate function.Matt Arsenault2014-03-242-39/+59
| | | | llvm-svn: 204651
* R600/SI: Fix 64-bit private loads.Matt Arsenault2014-03-241-1/+17
| | | | llvm-svn: 204630
* R600/SI: Fix warning with gcc 4.8.2Tom Stellard2014-03-241-1/+1
| | | | llvm-svn: 204618
* R600/SI: Promote fp64 SELECT to i64Tom Stellard2014-03-242-12/+2
| | | | | | | This type promotion is replacing a Tablegen pattern and it is already covered by existing tests. llvm-svn: 204617
* R600: Reorganize tablegen instruction definitionsTom Stellard2014-03-245-781/+826
| | | | | | Each GPU family now has its own file. llvm-svn: 204615
* R600/SI: Move instruction patterns to scalar versions.Matt Arsenault2014-03-212-38/+45
| | | | | | | Some of them also had the pattern on both, so this removes the duplication. llvm-svn: 204492
* R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()Tom Stellard2014-03-215-4/+150
| | | | llvm-svn: 204476
* R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()Tom Stellard2014-03-211-2/+50
| | | | llvm-svn: 204475
* R600/SI: Use SGPR_(32|64) reg clases when lowering SI_ADDR64_RSRCTom Stellard2014-03-211-4/+4
| | | | | | | | | | | | | | The SReg_(32|64) register classes contain special registers in addition to the numbered SGPRs. This can lead to machine verifier errors when these register classes are used as sub-registers for SReg_128, since SReg_128 only uses the numbered SGPRs. Replacing SReg_(32|64) with SGPR_(32|64) fixes this problem, since the SGPR_(32|64) register classes contain only numbered SGPRs. Tests cases for this are comming in a later commit. llvm-svn: 204474
* R600: Remove unused method declaration.Matt Arsenault2014-03-201-6/+0
| | | | llvm-svn: 204357
* R600/SI: Add unused LDS 2 form instructions.Matt Arsenault2014-03-192-1/+35
| | | | llvm-svn: 204275
* R600/SI: Add support for 64-bit LDS writesMatt Arsenault2014-03-191-1/+4
| | | | llvm-svn: 204274
* R600/SI: Add support for 64-bit LDS loads.Matt Arsenault2014-03-191-0/+2
| | | | | | | v2: -Use correct opcode for DS_READ_64 llvm-svn: 204273
* R600/SI: Match i16 immediate offset of LDS instructions.Matt Arsenault2014-03-192-20/+39
| | | | llvm-svn: 204272
* R600/SI: Don't display the GDS bit.Matt Arsenault2014-03-191-3/+3
| | | | | | | | It isn't actually used now, and probably never will be, plus it makes tests less annoying. I also think SC prints GDS instructions as a separate instruction name. llvm-svn: 204270
* R600/SI: Merge offset0 and offset1 fields for single address DS instructions v2Matt Arsenault2014-03-192-18/+27
| | | | | | | | | Also remove unused data fields from the DS_Load_Helper class. v2: - Merge fields for DS_WRITE llvm-svn: 204269
* Make methods staticMatt Arsenault2014-03-171-23/+24
| | | | llvm-svn: 204085
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-179-47/+154
| | | | llvm-svn: 204072
* R600/SI: Fix implementation of isInlineConstant() used by the verifierTom Stellard2014-03-171-14/+25
| | | | | | | | The type of the immediates should not matter as long as the encoding is equivalent to the encoding of one of the legal inline constants. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 204056
* R600/SI: Use correct dest register class for V_READFIRSTLANE_B32Tom Stellard2014-03-174-6/+28
| | | | | | | | | | | | This instructions writes to an 32-bit SGPR. This change required adding the 32-bit VCC_LO and VCC_HI registers, because the full VCC register is 64 bits. This fixes verifier errors on several of the indirect addressing piglit tests. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 204055
* R600/SI: Add generic checks to SIInstrInfo::verifyInstruction()Tom Stellard2014-03-171-0/+41
| | | | | | | Added checks for number of operands and operand register classes. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 204054
* R600: Remove unnecessary attempt to zext a pointer.Matt Arsenault2014-03-151-3/+6
| | | | | | Private pointers are now always 32-bits. llvm-svn: 203989
* R600: Code cleanup.Matt Arsenault2014-03-151-11/+12
| | | | | | | Use sign_extend_inreg and getZeroExtendInReg instead of using the bit operations they expand into. llvm-svn: 203988
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-133-11/+12
| | | | | | | | | | operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
* R600: LDS instructions shouldn't implicitly define OQAPTom Stellard2014-03-131-2/+0
| | | | | | | | | LDS instructions are pseudo instructions which model the OQAP defs and uses within a single instruction. This fixes a hang in the opencv MedianFilter tests. llvm-svn: 203818
* R600: Fix trunc store from i64 to i1Matt Arsenault2014-03-121-0/+6
| | | | llvm-svn: 203695
* R600: Calculate store mask instead of using switch.Matt Arsenault2014-03-111-17/+3
| | | | llvm-svn: 203527
* Remove incomplete commentMatt Arsenault2014-03-111-2/+0
| | | | llvm-svn: 203518
* Move trivial getter into header.Matt Arsenault2014-03-112-7/+4
| | | | llvm-svn: 203517
* Use .data() instead of &x[0]Matt Arsenault2014-03-111-2/+2
| | | | llvm-svn: 203516
* Fix indentationMatt Arsenault2014-03-111-9/+8
| | | | llvm-svn: 203515
* [TTI] There is actually no realistic way to pop TTI implementations offChandler Carruth2014-03-101-2/+0
| | | | | | | | | | | | | | the stack of the analysis group because they are all immutable passes. This is made clear by Craig's recent work to use override systematically -- we weren't overriding anything for 'finalizePass' because there is no such thing. This is kind of a lame restriction on the API -- we can no longer push and pop things, we just set up the stack and run. However, I'm not invested in building some better solution on top of the existing (terrifying) immutable pass and legacy pass manager. llvm-svn: 203437
* R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCCTom Stellard2014-03-072-8/+10
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 203281
* R600/SI: Custom lower i1 storesTom Stellard2014-03-071-0/+6
| | | | | | | | These are sometimes created by the shrink to boolean optimization in the globalopt pass. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 203280
* R600: Fix extloads from i8 / i16 to i64.Matt Arsenault2014-03-062-2/+17
| | | | | | | This appears to only be working for global loads. Private and local break for other reasons. llvm-svn: 203135
* R600/SI: Expand selects on vectors.Matt Arsenault2014-03-061-0/+2
| | | | llvm-svn: 203134
* Fix missing C++ mode commentMatt Arsenault2014-03-061-1/+1
| | | | llvm-svn: 203133
* [Layering] Move InstVisitor.h into the IR library as it is prettyChandler Carruth2014-03-062-2/+2
| | | | | | obviously coupled to the IR. llvm-svn: 203064
* Fix typoMatt Arsenault2014-03-051-3/+3
| | | | llvm-svn: 203013
* [Modules] Move ValueMap to the IR library. While this class does notChandler Carruth2014-03-041-1/+1
| | | | | | | | | | | | directly care about the Value class (it is templated so that the key can be any arbitrary Value subclass), it is in fact concretely tied to the Value class through the ValueHandle's CallbackVH interface which relies on the key type being some Value subclass to establish the value handle chain. Ironically, the unittest is already in the right library. llvm-svn: 202824
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-026-17/+17
| | | | | | Remove the old functions. llvm-svn: 202636
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-022-10/+10
| | | | llvm-svn: 202621
* Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.Craig Topper2014-03-021-1/+1
| | | | llvm-svn: 202618
* R600: Verify all instructions in the AsmPrinter on debug buildsTom Stellard2014-02-281-0/+7
| | | | | | | Make a call to R600's implementation of verifyInstruction() to check that instructions are only using legal operands. llvm-svn: 202544
* R600/SI: Expand all v16[if]32 operationsTom Stellard2014-02-281-1/+1
| | | | llvm-svn: 202543
* Remove MCPureStreamer.Rafael Espindola2014-02-271-2/+0
| | | | | | | We moved MCJIT to use native object formats a long time ago and R600 now uses ELF, so it was dead. llvm-svn: 202408
* R600/SI: Optimize SI_KILL for constant operandsMichel Danzer2014-02-272-6/+17
| | | | | | | | If the SI_KILL operand is constant, we can either clear the exec mask if the operand is negative, or do nothing otherwise. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 202337
* R600/SI: Allow SI_KILL for geometry shadersMichel Danzer2014-02-271-3/+7
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 202336
* R600: Remove unnecessary build_vector pattern.Matt Arsenault2014-02-262-10/+1
| | | | | | It is already fully handled in AMDGPUISelDAGToDAG. llvm-svn: 202312
* R600: Don't unconditionally unroll loops with private memory accessesTom Stellard2014-02-251-3/+7
| | | | | | | This causes the size of the scrypt kernel to explode and eats all the memory on some systems. llvm-svn: 202195
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