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path: root/llvm/lib/Target/R600/SIRegisterInfo.cpp
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* R600/SI: Return the correct index for VGPRs in getHWRegIndex()Tom Stellard2014-03-311-1/+1
| | | | | | The register index is stored in the low 8-bits of the encoding. llvm-svn: 205186
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-181-0/+2
| | | | | | | Moving into a VSrc doesn't always work, since it could be replaced with an SGPR later. llvm-svn: 195042
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+1
| | | | | | This fixes a crash with GNOME settings manager. llvm-svn: 194836
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-0/+8
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-131-6/+42
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* Make method staticMatt Arsenault2013-11-101-1/+1
| | | | llvm-svn: 194340
* R600/SI: Mark the EXEC register as reservedTom Stellard2013-10-101-0/+1
| | | | | | | | This prevents the machine verifier from complaining about uses of an undefined physical register. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192364
* R600/SI: Choose the correct MOV instruction for copying immediatesTom Stellard2013-08-141-0/+11
| | | | | | | | The instruction selector will now try to infer the destination register so it can decided whether to use V_MOV_B32 or S_MOV_B32 when copying immediates. llvm-svn: 188426
* R600/SI: Add more special cases for opcodes to ensureSRegLimit()Tom Stellard2013-08-061-0/+21
| | | | | | Also factor out the register class lookup to its own function. llvm-svn: 187830
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-5/+3
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600/SI: switch back to RegPressure schedulingChristian Konig2013-03-261-0/+5
| | | | | Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 178021
* Add R600 backendTom Stellard2012-12-111-0/+48
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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