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path: root/llvm/lib/Target/R600/SIInstructions.td
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* R600/SI: Re-order MUBUF operands to match asm strings.Tom Stellard2015-03-101-8/+8
* R600/SI: Add 32-bit encoding of v_cndmask_b32Tom Stellard2015-03-101-6/+15
* R600/SI: Move gds operand to the end of operand listTom Stellard2015-03-091-9/+9
* R600/SI: Refactor DS instruction defsTom Stellard2015-03-091-19/+29
* R600/SI: Fix DS definitions and add missing instructionsTom Stellard2015-03-091-42/+79
* R600/SI: Fix opcode for ds_read2_b64 and ds_read2st64_b64Tom Stellard2015-03-091-2/+2
* R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32Marek Olsak2015-03-041-1/+3
* R600/SI: Add missing mubuf instructionsTom Stellard2015-02-271-8/+24
* R600/SI: Consistently put soffset before the offset operand for mubuf instruc...Tom Stellard2015-02-271-3/+3
* R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructionsTom Stellard2015-02-271-2/+3
* R600/SI: Fix mad*k definitionsMatt Arsenault2015-02-211-2/+2
* R600/SI: Remove v_sub_f64 pseudoMatt Arsenault2015-02-201-11/+0
* R600: Use new fmad node.Matt Arsenault2015-02-201-3/+0
* R600/SI: Fix READLANE and WRITELANE lane select for VIMarek Olsak2015-02-181-4/+4
* R600/SI: Add missing VOP1 instructionsTom Stellard2015-02-181-5/+15
* R600/SI: Add missing VOP2 instructionsTom Stellard2015-02-181-2/+9
* R600/SI: Add definition for S_CBRANCH_G_FORKTom Stellard2015-02-181-1/+7
* R600/SI: Add missing SOP1 instructionsTom Stellard2015-02-181-12/+12
* R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64Matt Arsenault2015-02-181-1/+1
* R600/SI: Add missing offset operand to buffer bothenMatt Arsenault2015-02-181-2/+2
* R600/SI: Implement correct f64 fdivMatt Arsenault2015-02-141-10/+7
* R600/SI: Fix implicit vcc operand to v_div_fmas_*Matt Arsenault2015-02-141-3/+16
* R600/SI: Fix schedule model for v_div_scale_{f32|f64}Matt Arsenault2015-02-141-1/+3
* R600/SI: Add soffset operand to mubuf addr64 instructionTom Stellard2015-02-111-2/+2
* R600/SI: Also enable WQM for image opcodes which calculate LOD v3Michel Danzer2015-02-061-32/+32
* R600/SI: Fix i64 truncate to i1Matt Arsenault2015-02-051-0/+6
* R600/SI: Remove useless patterns in VALU which are already covered by SALUMarek Olsak2015-02-031-45/+16
* R600/SI: Fix B64 VALU shifts on VIMarek Olsak2015-02-031-0/+14
* R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VIMarek Olsak2015-02-031-5/+5
* R600/SI: Remove VOP2_REV definitions from target-specific instructionsMarek Olsak2015-02-031-6/+3
* R600/SI: Trivial instruction definition corrections for VI (v2)Marek Olsak2015-02-031-12/+23
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-5/+5
* R600/SI: Fix MIN3/MAX3 on VI, define MED3Marek Olsak2015-01-271-9/+16
* R600/SI: Add VI versions of LDS atomicsMarek Olsak2015-01-271-73/+73
* R600/SI: Add VI versions of MUBUF atomicsMarek Olsak2015-01-271-42/+38
* R600/SI: Add VI versions of MUBUF loads and storesMarek Olsak2015-01-271-36/+23
* R600/SI: Use external symbols for scratch bufferTom Stellard2015-01-201-4/+4
* R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32Matt Arsenault2015-01-151-2/+4
* R600/SI: Unify VOP2 instructions which are VOP3-only on VIMarek Olsak2015-01-151-12/+11
* R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VIMarek Olsak2015-01-151-1/+1
* R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VIMarek Olsak2015-01-151-11/+11
* R600/SI: Don't select SI-only VOP3 opcodes on VIMarek Olsak2015-01-151-17/+20
* R600/SI: Spill VGPRs to scratch space for compute shadersTom Stellard2015-01-141-23/+28
* R600/SI: Define a schedule modelTom Stellard2015-01-141-3/+51
* R600/SI: Add pattern for bitcasting fp immediates to integersTom Stellard2015-01-131-3/+3
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-94/+94
* R600/SI: Add a V_MOV_B64 pseudo instructionTom Stellard2015-01-071-0/+6
* R600/SI: Add class intrinsicMatt Arsenault2015-01-061-4/+4
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-0/+5
* R600: Fix min/max matching problems with unordered comparesMatt Arsenault2014-12-121-0/+2
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