index
:
bcm5719-llvm
meklort-10.0.0
meklort-10.0.1
ortega-7.0.1
Project Ortega BCM5719 LLVM
Raptor Computing Systems
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
llvm
/
lib
/
Target
/
R600
/
SIInstructions.td
Commit message (
Expand
)
Author
Age
Files
Lines
*
R600/SI: Re-order MUBUF operands to match asm strings.
Tom Stellard
2015-03-10
1
-8
/
+8
*
R600/SI: Add 32-bit encoding of v_cndmask_b32
Tom Stellard
2015-03-10
1
-6
/
+15
*
R600/SI: Move gds operand to the end of operand list
Tom Stellard
2015-03-09
1
-9
/
+9
*
R600/SI: Refactor DS instruction defs
Tom Stellard
2015-03-09
1
-19
/
+29
*
R600/SI: Fix DS definitions and add missing instructions
Tom Stellard
2015-03-09
1
-42
/
+79
*
R600/SI: Fix opcode for ds_read2_b64 and ds_read2st64_b64
Tom Stellard
2015-03-09
1
-2
/
+2
*
R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32
Marek Olsak
2015-03-04
1
-1
/
+3
*
R600/SI: Add missing mubuf instructions
Tom Stellard
2015-02-27
1
-8
/
+24
*
R600/SI: Consistently put soffset before the offset operand for mubuf instruc...
Tom Stellard
2015-02-27
1
-3
/
+3
*
R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructions
Tom Stellard
2015-02-27
1
-2
/
+3
*
R600/SI: Fix mad*k definitions
Matt Arsenault
2015-02-21
1
-2
/
+2
*
R600/SI: Remove v_sub_f64 pseudo
Matt Arsenault
2015-02-20
1
-11
/
+0
*
R600: Use new fmad node.
Matt Arsenault
2015-02-20
1
-3
/
+0
*
R600/SI: Fix READLANE and WRITELANE lane select for VI
Marek Olsak
2015-02-18
1
-4
/
+4
*
R600/SI: Add missing VOP1 instructions
Tom Stellard
2015-02-18
1
-5
/
+15
*
R600/SI: Add missing VOP2 instructions
Tom Stellard
2015-02-18
1
-2
/
+9
*
R600/SI: Add definition for S_CBRANCH_G_FORK
Tom Stellard
2015-02-18
1
-1
/
+7
*
R600/SI: Add missing SOP1 instructions
Tom Stellard
2015-02-18
1
-12
/
+12
*
R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64
Matt Arsenault
2015-02-18
1
-1
/
+1
*
R600/SI: Add missing offset operand to buffer bothen
Matt Arsenault
2015-02-18
1
-2
/
+2
*
R600/SI: Implement correct f64 fdiv
Matt Arsenault
2015-02-14
1
-10
/
+7
*
R600/SI: Fix implicit vcc operand to v_div_fmas_*
Matt Arsenault
2015-02-14
1
-3
/
+16
*
R600/SI: Fix schedule model for v_div_scale_{f32|f64}
Matt Arsenault
2015-02-14
1
-1
/
+3
*
R600/SI: Add soffset operand to mubuf addr64 instruction
Tom Stellard
2015-02-11
1
-2
/
+2
*
R600/SI: Also enable WQM for image opcodes which calculate LOD v3
Michel Danzer
2015-02-06
1
-32
/
+32
*
R600/SI: Fix i64 truncate to i1
Matt Arsenault
2015-02-05
1
-0
/
+6
*
R600/SI: Remove useless patterns in VALU which are already covered by SALU
Marek Olsak
2015-02-03
1
-45
/
+16
*
R600/SI: Fix B64 VALU shifts on VI
Marek Olsak
2015-02-03
1
-0
/
+14
*
R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI
Marek Olsak
2015-02-03
1
-5
/
+5
*
R600/SI: Remove VOP2_REV definitions from target-specific instructions
Marek Olsak
2015-02-03
1
-6
/
+3
*
R600/SI: Trivial instruction definition corrections for VI (v2)
Marek Olsak
2015-02-03
1
-12
/
+23
*
Reuse a bunch of cached subtargets and remove getSubtarget calls
Eric Christopher
2015-01-30
1
-5
/
+5
*
R600/SI: Fix MIN3/MAX3 on VI, define MED3
Marek Olsak
2015-01-27
1
-9
/
+16
*
R600/SI: Add VI versions of LDS atomics
Marek Olsak
2015-01-27
1
-73
/
+73
*
R600/SI: Add VI versions of MUBUF atomics
Marek Olsak
2015-01-27
1
-42
/
+38
*
R600/SI: Add VI versions of MUBUF loads and stores
Marek Olsak
2015-01-27
1
-36
/
+23
*
R600/SI: Use external symbols for scratch buffer
Tom Stellard
2015-01-20
1
-4
/
+4
*
R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
Matt Arsenault
2015-01-15
1
-2
/
+4
*
R600/SI: Unify VOP2 instructions which are VOP3-only on VI
Marek Olsak
2015-01-15
1
-12
/
+11
*
R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI
Marek Olsak
2015-01-15
1
-1
/
+1
*
R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
Marek Olsak
2015-01-15
1
-11
/
+11
*
R600/SI: Don't select SI-only VOP3 opcodes on VI
Marek Olsak
2015-01-15
1
-17
/
+20
*
R600/SI: Spill VGPRs to scratch space for compute shaders
Tom Stellard
2015-01-14
1
-23
/
+28
*
R600/SI: Define a schedule model
Tom Stellard
2015-01-14
1
-3
/
+51
*
R600/SI: Add pattern for bitcasting fp immediates to integers
Tom Stellard
2015-01-13
1
-3
/
+3
*
R600/SI: Remove VReg_32 register class
Tom Stellard
2015-01-07
1
-94
/
+94
*
R600/SI: Add a V_MOV_B64 pseudo instruction
Tom Stellard
2015-01-07
1
-0
/
+6
*
R600/SI: Add class intrinsic
Matt Arsenault
2015-01-06
1
-4
/
+4
*
R600/SI: Fix f64 inline immediates
Matt Arsenault
2014-12-17
1
-0
/
+5
*
R600: Fix min/max matching problems with unordered compares
Matt Arsenault
2014-12-12
1
-0
/
+2
[next]