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path: root/llvm/lib/Target/R600/SIInstrInfo.cpp
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* R600/SI: Fix verifier error when producing v_madmk_f32Matt Arsenault2015-04-241-0/+3
* R600/SI: Special case v_mov_b32 as really rematerializableMatt Arsenault2015-04-231-0/+14
* R600/SI: Improve BFM supportMarek Olsak2015-03-241-0/+1
* R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SIMarek Olsak2015-03-241-0/+20
* R600/SI: Merge tables for commutingMatt Arsenault2015-03-231-20/+0
* R600/SI: Allow commuting comparesMatt Arsenault2015-03-231-2/+24
* R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2015-03-231-2/+10
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-29/+6
* R600/SI: Re-order MUBUF operands to match asm strings.Tom Stellard2015-03-101-4/+3
* R600/SI: Move kill flag to second instruction when splitting SMRDTom Stellard2015-03-101-5/+12
* R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32Marek Olsak2015-03-041-0/+1
* Make some non-constant static variables non-static or fully const.Benjamin Kramer2015-03-011-4/+1
* R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructionsTom Stellard2015-02-271-1/+7
* R600/SI: Use v_madmk_f32Matt Arsenault2015-02-211-4/+51
* R600/SI: Try to use v_madak_f32Matt Arsenault2015-02-211-0/+78
* R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_CMarek Olsak2015-02-181-8/+6
* R600/SI: Remove explicit VOP operand checkingMarek Olsak2015-02-181-28/+0
* R600/SI: Fix brace identationMatt Arsenault2015-02-181-1/+1
* R600/SI: Fix copies from SGPR to VCCMatt Arsenault2015-02-141-5/+10
* R600/SI: Add hack to copy from a VGPR to VCCMatt Arsenault2015-02-141-0/+10
* R600/SI: Allow f64 inline immediates in i64 operandsMatt Arsenault2015-02-131-21/+41
* R600/SI: Remove unnecessary check for fpimmMatt Arsenault2015-02-131-1/+1
* R600/SI: Add soffset operand to mubuf addr64 instructionTom Stellard2015-02-111-3/+2
* R600/SI: Fix B64 VALU shifts on VIMarek Olsak2015-02-031-0/+18
* R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VIMarek Olsak2015-02-031-2/+6
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-3/+2
* R600/SI: Add subtarget feature to enable VGPR spilling for all shader typesTom Stellard2015-01-201-11/+3
* R600/SI: Use external symbols for scratch bufferTom Stellard2015-01-201-2/+2
* R600/SI: Update SIInstrInfo:verifyInstruction() after r225662Tom Stellard2015-01-201-6/+12
* R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VIMarek Olsak2015-01-151-3/+3
* R600/SI: Don't shrink instructions whose e32 encoding doesn't existMarek Olsak2015-01-151-1/+5
* R600/SI: Use IMPLICIT_DEF and KILL when failing to spill VGPRsTom Stellard2015-01-141-3/+2
* R600/SI: Spill VGPRs to scratch space for compute shadersTom Stellard2015-01-141-9/+17
* R600/SI: Add pattern for bitcasting fp immediates to integersTom Stellard2015-01-131-18/+14
* R600/SI: Use RegisterOperands to specify which operands can accept immediatesTom Stellard2015-01-121-2/+2
* R600/SI: Commute instructions to enable more folding opportunitiesTom Stellard2015-01-071-1/+4
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-11/+11
* R600/SI: Add a V_MOV_B64 pseudo instructionTom Stellard2015-01-071-0/+31
* R600/SI: Teach SIFoldOperands to split 64-bit constants when foldingTom Stellard2015-01-071-0/+10
* R600/SI: isLegalOperand() shouldn't check constant bus for SALU instructionsTom Stellard2014-12-191-1/+1
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-12/+26
* R600/SI: Handle physical registers in getOpRegClassMatt Arsenault2014-12-111-2/+7
* R600/SI: Don't verify constant bus usage of flag opsMatt Arsenault2014-12-111-2/+10
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-071-13/+23
* R600/SI: Update instruction conversions for VIMarek Olsak2014-12-071-0/+27
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-021-4/+14
* R600/SI: Various instruction format bit test cleanupsMatt Arsenault2014-12-011-52/+0
* R600/SI: Add an s_mov_b32 to patterns which use the M0RegClassTom Stellard2014-11-211-20/+0
* R600/SI: Make SIInstrInfo::isOperandLegal() more strictTom Stellard2014-11-191-1/+10
* R600/SI: Implement areMemAccessesTriviallyDisjointMatt Arsenault2014-11-191-0/+83
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