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path: root/llvm/lib/Target/R600/SIDefines.h
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* R600 -> AMDGPU renameTom Stellard2015-06-131-172/+0
| | | | llvm-svn: 239657
* R600/SI: Fix bug in VGPR spillingTom Stellard2015-05-121-1/+2
| | | | | | | | | | | | AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which caused the srsrc and soffset register to not be set correctly. This commit replaces the switch statement with a SITargetInfo query to make sure all spill instructions are covered. Differential Revision: http://reviews.llvm.org/D9582 llvm-svn: 237164
* R600/SI: Also enable WQM for image opcodes which calculate LOD v3Michel Danzer2015-02-061-1/+2
| | | | | | | | | | | | | If whole quad mode isn't enabled for these, the level of detail is calculated incorrectly for pixels along diagonal triangle edges, causing artifacts. v2: Use a TSFlag instead of lots of switch cases v3: Add test coverage Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642 Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 228372
* R600/SI: Add subtarget feature to enable VGPR spilling for all shader typesTom Stellard2015-01-201-0/+3
| | | | | | | This is disabled by default, but can be enabled with the subtarget feature: 'vgpr-spilling' llvm-svn: 226597
* R600/SI: Use external symbols for scratch bufferTom Stellard2015-01-201-0/+1
| | | | | | | | We were passing the scratch buffer address to the shaders via user sgprs, but now we use external symbols and have the driver patch the shader using reloc information. llvm-svn: 226586
* R600/SI: Use RegisterOperands to specify which operands can accept immediatesTom Stellard2015-01-121-0/+13
| | | | | | | | | | | | There are some operands which can take either immediates or registers and we were previously using different register class to distinguish between operands that could take immediates and those that could not. This patch switches to using RegisterOperands which should simplify the backend by reducing the number of register classes and also make it easier to implement the assembler. llvm-svn: 225662
* R600/SI: Add class intrinsicMatt Arsenault2015-01-061-0/+15
| | | | llvm-svn: 225305
* R600/SI: Move more information into SIProgramInfo structTom Stellard2014-12-021-1/+8
| | | | llvm-svn: 223154
* R600/SI: Various instruction format bit test cleanupsMatt Arsenault2014-12-011-10/+20
| | | | | | | | | | | - Fix missing SALU format bits - Remove unused isSALUInstr - Add isVALU - Switch isDS to use a bit like the others - Move SIInstrInfo::is* functions to header - Reorder so they are approximately sorted by type (SALU, VALU, memory) llvm-svn: 223038
* R600/SI: Fix printing of clamp and omodMatt Arsenault2014-09-301-0/+9
| | | | | | | | No tests for omod since nothing uses it yet, but this should get rid of the remaining annoying trailing zeros after some instructions. llvm-svn: 218692
* R600/SI: Fix hardcoded values for modifiers.Matt Arsenault2014-09-291-0/+16
| | | | | | Move enums to SIDefines.h llvm-svn: 218610
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-1/+2
| | | | llvm-svn: 217777
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* R600/SI: Add isMUBUF / isMTBUFMatt Arsenault2014-07-291-1/+4
| | | | | | Also add missing comments about how the flags work. llvm-svn: 214195
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-0/+4
| | | | llvm-svn: 213551
* R600/SI: Add FP mode bits to binary.Matt Arsenault2014-06-261-0/+50
| | | | | | | | The default rounding mode to initialize the mode register needs to be reported to the runtime. Fill in other bits a kernel may be interested in setting for future use. llvm-svn: 211791
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-131-1/+2
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*Tom Stellard2013-10-101-1/+5
| | | | | | | The function is used by the machine verifier and checks that VOP* instructions have legal operands. llvm-svn: 192367
* R600/SI: Fix broken encoding of DS_WRITE_B32Michel Danzer2013-08-161-1/+2
| | | | | | | | | | | | | | The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused it to corrupt the encoding of that by clobbering the first operand with the second one. Undo that damage and only apply the SMRD logic to that. Fixes some derivates related piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188558
* R600/SI: Assign a register class to the $vaddr operand for MIMG instructionsTom Stellard2013-08-141-0/+6
| | | | | | | The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. llvm-svn: 188425
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-0/+4
| | | | | | | Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
* R600/SI: Emit config values in register value pairs.Tom Stellard2013-04-151-0/+22
Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546
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