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path: root/llvm/lib/Target/R600/R600RegisterInfo.h
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* R600 -> AMDGPU renameTom Stellard2015-06-131-49/+0
| | | | llvm-svn: 239657
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-1/+1
| | | | | | classes. llvm-svn: 231954
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-6/+0
| | | | | | Most of these are no longer used any more. llvm-svn: 210915
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-4/+2
| | | | llvm-svn: 210869
* De-virtualize or remove some methods that have no overrides nor override ↵Craig Topper2014-04-301-1/+1
| | | | | | anything. In some cases remove all together if there are no callers either. llvm-svn: 207610
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-7/+8
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 194755
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-0/+2
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2Tom Stellard2013-08-141-4/+0
| | | | | | | | | | | | Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. llvm-svn: 188427
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-3/+1
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-171-0/+3
| | | | llvm-svn: 182129
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-1/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* Add R600 backendTom Stellard2012-12-111-0/+55
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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