| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | R600: Simplify handling of private address space | Tom Stellard | 2013-10-22 | 1 | -6/+1 |
| * | R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 | Tom Stellard | 2013-08-14 | 1 | -10/+0 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 1 | -6/+5 |
| * | R600: Use bottom up scheduling algorithm | Vincent Lejeune | 2013-05-17 | 1 | -1/+5 |
| * | R600: Mark all members of the TRegMem register class as reserved | Tom Stellard | 2013-02-19 | 1 | -0/+6 |
| * | R600: Consolidate sub register indices. | Tom Stellard | 2013-02-07 | 1 | -4/+4 |
| * | R600: Support for indirect addressing v4 | Tom Stellard | 2013-02-06 | 1 | -0/+14 |
| * | R600: improve inputs/interpolation handling | Tom Stellard | 2013-02-05 | 1 | -6/+0 |
| * | R600: rework handling of the constants | Tom Stellard | 2013-01-23 | 1 | -5/+1 |
| * | Add R600 backend | Tom Stellard | 2012-12-11 | 1 | -0/+89 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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