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path: root/llvm/lib/Target/R600/R600Instructions.td
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* R600: Reorganize tablegen instruction definitionsTom Stellard2014-03-241-781/+2
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-171-6/+11
* R600: LDS instructions shouldn't implicitly define OQAPTom Stellard2014-03-131-2/+0
* R600: Remove unnecessary build_vector pattern.Matt Arsenault2014-02-261-3/+0
* Fix known typosAlp Toker2014-01-241-1/+1
* R600: Disable the BFE patternTom Stellard2014-01-231-1/+3
* R600: Add some missing CF instruction definitions to the .td files.Tom Stellard2014-01-221-0/+7
* R600: CF_PUSH is the same on Evergreen and CaymanTom Stellard2014-01-221-3/+4
* R600: MOVA is vector onlyTom Stellard2014-01-221-1/+1
* R600: Allow ftruncTom Stellard2013-12-201-0/+3
* R600: Workaround for cayman loop bugVincent Lejeune2013-12-021-0/+4
* R600: Add support for ISD::FROUNDTom Stellard2013-11-271-4/+14
* R600/SI: Fixing handling of condition codesTom Stellard2013-11-221-3/+3
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-1/+0
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-111-1/+1
* R600: Clear the VPM bit of export instructions.Vincent Lejeune2013-10-131-4/+4
* R600: Add a ldptr intrinsic to support MSAA.Vincent Lejeune2013-10-021-0/+4
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-011-0/+1
* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-011-1/+1
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-281-43/+11
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-281-48/+0
* R600: Add support for LDS atomic subtractAaron Watry2013-09-061-0/+4
* R600: Add support for local memory atomic addTom Stellard2013-09-051-7/+35
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-041-20/+6
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-0/+12
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-3/+21
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-161-0/+13
* R600: Add support for v4i32 stores on CaymanTom Stellard2013-08-161-0/+1
* R600: Add IsExport bit to TableGen instruction definitionsTom Stellard2013-08-161-0/+3
* R600: Change the RAT instruction assembly names so they match the docsTom Stellard2013-08-161-30/+33
* R600/SI: Handle MSAA texture targetsTom Stellard2013-08-141-1/+15
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-5/+75
* Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"Tom Stellard2013-07-311-6/+20
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-07-311-20/+6
* R600: Remove predicated_break instVincent Lejeune2013-07-311-3/+0
* R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessaryTom Stellard2013-07-231-19/+0
* R600: Add support for 24-bit MAD instructionsTom Stellard2013-07-231-0/+6
* R600: Add support for 24-bit MUL instructionsTom Stellard2013-07-231-0/+7
* R600: Improve support for < 32-bit loadsTom Stellard2013-07-231-0/+8
* R600: Use KCache for kernel argumentsTom Stellard2013-07-231-1/+1
* R600: Clean up extended load patternsTom Stellard2013-07-231-8/+8
* R600: Don't emit empty then clause and use alu_pop_afterVincent Lejeune2013-07-191-0/+1
* R600: Do not predicated basic block with multiple alu clauseVincent Lejeune2013-07-091-1/+1
* R600: Use DAG lowering pass to handle fcos/fsinVincent Lejeune2013-07-091-22/+10
* R600: Print Export SwizzleVincent Lejeune2013-07-091-2/+2
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-291-0/+2
* R600: Add local memory support via LDSTom Stellard2013-06-281-0/+75
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-281-0/+30
* R600: Add ALUInst bit to tablegen definitions v2Tom Stellard2013-06-281-0/+3
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-251-4/+12
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