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path: root/llvm/lib/Target/R600/R600ISelLowering.cpp
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* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-271-1/+3
| | | | llvm-svn: 204945
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-171-0/+5
| | | | llvm-svn: 204072
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-4/+4
| | | | | | Remove the old functions. llvm-svn: 202636
* Fix known typosAlp Toker2014-01-241-3/+3
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* R600/SI: Add support for i8 and i16 private loads/storesTom Stellard2014-01-221-0/+13
| | | | llvm-svn: 199823
* Use llvm_unreachable instead of assert(0)Matt Arsenault2013-12-101-2/+2
| | | | llvm-svn: 196971
* R600: Fix an infinite loop when trying to reorganize export/tex vector inputVincent Lejeune2013-12-101-5/+8
| | | | llvm-svn: 196923
* Correct word hyphenationsAlp Toker2013-12-051-1/+1
| | | | | | | This patch tries to avoid unrelated changes other than fixing a few hyphen-related ambiguities and contractions in nearby lines. llvm-svn: 196471
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-12/+8
| | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 194755
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-15/+0
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-131-1/+9
| | | | llvm-svn: 194547
* R600: Reenable llvm.R600.load.input/interp.input for compatibilityVincent Lejeune2013-11-121-0/+45
| | | | llvm-svn: 194484
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-111-37/+18
| | | | llvm-svn: 194425
* Use isa<> instead of dyn_cast<> with unused valueMatt Arsenault2013-11-011-3/+3
| | | | llvm-svn: 193869
* Fix a few typosMatt Arsenault2013-10-301-7/+7
| | | | llvm-svn: 193723
* Prune utf8 chars in comments.NAKAMURA Takumi2013-10-281-2/+2
| | | | llvm-svn: 193512
* Target/R600: Un-tab-ify.NAKAMURA Takumi2013-10-281-3/+3
| | | | llvm-svn: 193510
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-231-8/+15
| | | | | | | | | | The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. llvm-svn: 193215
* R600: Use masked read sel for texture instructionsVincent Lejeune2013-10-131-0/+5
| | | | llvm-svn: 192554
* R600: fix swizzle exportVincent Lejeune2013-10-131-5/+9
| | | | llvm-svn: 192553
* R600: Add a ldptr intrinsic to support MSAA.Vincent Lejeune2013-10-021-1/+5
| | | | llvm-svn: 191838
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-281-1/+8
| | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 191603
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-281-4/+12
| | | | | | | | | | | SelectionDAG will now attempt to inverse an illegal conditon in order to find a legal one and if that doesn't work, it will attempt to swap the operands using the inverted condition. There are no new test cases for this, but a nubmer of the existing R600 tests hit this path. llvm-svn: 191602
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-281-28/+58
| | | | | | | | | | | | This is useful for targets like R600, which only support GT, GE, NE, and EQ condition codes as it removes the need to handle unsupported condition codes in target specific code. There are no tests with this commit, but R600 has been updated to take advantage of this new feature, so its existing selectcc tests are now testing the swapped operands path. llvm-svn: 191601
* R600: Move clamp handling code to R600IselLowering.cppVincent Lejeune2013-09-121-0/+16
| | | | llvm-svn: 190645
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-121-4/+59
| | | | llvm-svn: 190644
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-121-0/+179
| | | | | | | This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643
* R600: Add support for local memory atomic addTom Stellard2013-09-051-7/+15
| | | | llvm-svn: 190080
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-051-14/+6
| | | | llvm-svn: 190079
* R600: Add support for vector local memory loadsTom Stellard2013-08-261-0/+8
| | | | llvm-svn: 189226
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-14/+15
| | | | llvm-svn: 189225
* R600: Add support for v4i32 and v2i32 local storesTom Stellard2013-08-261-1/+1
| | | | llvm-svn: 189222
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-161-9/+0
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188596
* R600: Add support for global vector stores with elements less than 32-bitsTom Stellard2013-08-161-1/+7
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188520
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-161-12/+49
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188519
* R600: Set scheduling preference to Sched::SourceTom Stellard2013-08-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | R600 doesn't need to do any scheduling on the SelectionDAG now that it has a very good MachineScheduler. Also, using the VLIW SelectionDAG scheduler was having a major impact on compile times. For example with the phatk kernel here are the LLVM IR to machine code compile times: With Sched::VLIW Total Compile Time: 1.4890 Seconds (User + System) SelectionDAG Instruction Scheduling: 1.1670 Seconds (User + System) With Sched::Source Total Compile Time: 0.3330 Seconds (User + System) SelectionDAG Instruction Scheduling: 0.0070 Seconds (User + System) The code ouput was identical with both schedulers. This may not be true for all programs, but it gives me confidence that there won't be much reduction, if any, in code quality by using Sched::Source. llvm-svn: 188215
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-3/+18
| | | | | | | | | | | | | | | | | * Added R600_Reg64 class * Added T#Index#.XY registers definition * Added v2i32 register reads from parameter and global space * Added f32 and i32 elements extraction from v2f32 and v2i32 * Added v2i32 -> v2f32 conversions Tom Stellard: - Mark vec2 operations as expand. The addition of a vec2 register class made them all legal. Patch by: Dmitry Cherkassov Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com> llvm-svn: 187582
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-301-4/+0
| | | | llvm-svn: 187421
* [R600] Replicate old DAGCombiner behavior in target specific DAG combine.Quentin Colombet2013-07-301-0/+56
| | | | | | | build_vector is lowered to REG_SEQUENCE, which is something the register allocator does a good job at optimizing. llvm-svn: 187397
* R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()Tom Stellard2013-07-231-0/+24
| | | | | | | | | | This increases the number of opportunites we have for folding. With the previous implementation we were unable to fold into any instructions other than the first when multiple instructions were selected from a single SDNode. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186919
* R600: Use KCache for kernel argumentsTom Stellard2013-07-231-31/+11
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186918
* R600: Use the same compute kernel calling convention for all GPUsTom Stellard2013-07-231-6/+15
| | | | | | | | A side-effect of this is that now the compiler expects kernel arguments to be 4-byte aligned. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186916
* R600: Use correct LoadExtType when lowering kernel argumentsTom Stellard2013-07-231-1/+9
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186915
* R600: Clean up extended load patternsTom Stellard2013-07-231-4/+4
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186914
* R600: Expand VSELECT for all typesTom Stellard2013-07-181-3/+0
| | | | llvm-svn: 186613
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-0/+2
| | | | | | | Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
* R600: Fix a rare bug where swizzle optimization returns wrong valuesVincent Lejeune2013-07-091-2/+3
| | | | llvm-svn: 185942
* R600: Use DAG lowering pass to handle fcos/fsinVincent Lejeune2013-07-091-1/+38
| | | | | NOTE: This is a candidate for the stable branch. llvm-svn: 185940
* R600: Add local memory support via LDSTom Stellard2013-06-281-2/+16
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-251-1/+1
| | | | llvm-svn: 184880
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