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path: root/llvm/lib/Target/R600/R600EmitClauseMarkers.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-336/+0
| | | | llvm-svn: 239657
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-2/+1
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-1/+3
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-2/+2
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
| | | | llvm-svn: 207197
* R600: Register R600EmitClauseMarkers passTom Stellard2013-12-111-7/+17
| | | | | | | This enables -print-before-all to dump MachineInstrs after it is run. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197056
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-5/+66
| | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 194755
* R600: Use StructurizeCFGPass for non SI targetsTom Stellard2013-10-101-0/+1
| | | | | | | | | | | | | | StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of shader from shadertoy (which exhibits complex control flow constructs) to works correctly with respect to CFG handling (and allow us to detect potential bug in other part of the backend). We provide a cmd line argument to disable the pass for debug purpose. Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192363
* R600: Put PRED_X instruction in its own clauseVincent Lejeune2013-10-011-0/+8
| | | | llvm-svn: 191789
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-1/+1
| | | | | | size. llvm-svn: 186274
* R600: Do not predicated basic block with multiple alu clauseVincent Lejeune2013-07-091-4/+10
| | | | | | | | | Test is not included as it is several 1000 lines long. To test this functionnality, a test case must generate at least 2 ALU clauses, where an ALU clause is ~110 instructions long. NOTE: This is a candidate for the stable branch. llvm-svn: 185943
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-281-1/+8
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185161
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+3
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-041-1/+5
| | | | llvm-svn: 183278
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-2/+4
| | | | | | while there. llvm-svn: 182594
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-171-4/+2
| | | | | | | | | | Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register coalescer to remove some unneeded COPY. This patch also defines some structures/functions that can be used to handle every vector instructions (CUBE, Cayman special instructions...) in a similar fashion. llvm-svn: 182126
* R600: Some factorizationVincent Lejeune2013-05-171-32/+13
| | | | llvm-svn: 182123
* R600: Fix last ALU of a clause being emitted in a separate clauseVincent Lejeune2013-04-031-2/+2
| | | | llvm-svn: 178675
* R600: Factorize maximum alu per clause in a single locationVincent Lejeune2013-04-031-1/+1
| | | | llvm-svn: 178667
* R600: Consider KILLGT as an ALU instructionVincent Lejeune2013-04-031-2/+4
| | | | | | | Mesa does not override llvm behavior wrt KILLGT anymore so llvm has to handle KILLGT on its own. llvm-svn: 178664
* R600: Emit CF_ALU and use true kcache register.Vincent Lejeune2013-04-011-0/+253
llvm-svn: 178503
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