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path: root/llvm/lib/Target/R600/R600Defines.h
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* R600 -> AMDGPU renameTom Stellard2015-06-131-171/+0
| | | | llvm-svn: 239657
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-1/+2
| | | | llvm-svn: 189223
* R600: Add IsExport bit to TableGen instruction definitionsTom Stellard2013-08-161-1/+2
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188516
* R600: Add local memory support via LDSTom Stellard2013-06-281-1/+5
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Add ALUInst bit to tablegen definitions v2Tom Stellard2013-06-281-1/+2
| | | | | | | | v2: - Remove functions left over from a previous rebase. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185160
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-251-40/+1
| | | | llvm-svn: 184880
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-171-0/+74
| | | | | | | | | | Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register coalescer to remove some unneeded COPY. This patch also defines some structures/functions that can be used to handle every vector instructions (CUBE, Cayman special instructions...) in a similar fashion. llvm-svn: 182126
* R600: Remove dead code from the CodeEmitter v2Tom Stellard2013-05-061-0/+3
| | | | | | | | | v2: - Replace switch statement with TSFlags query Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181229
* R600: Emit config values in register / value pairsTom Stellard2013-05-061-0/+26
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181228
* R600: Add a Bank Swizzle operandVincent Lejeune2013-04-301-5/+6
| | | | llvm-svn: 180758
* R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune2013-04-301-1/+3
| | | | | | v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache llvm-svn: 180755
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* R600: rework handling of the constantsTom Stellard2013-01-231-0/+15
| | | | | | | | | | | | | | | | | | | | Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173222
* Add R600 backendTom Stellard2012-12-111-0/+79
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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