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path: root/llvm/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-181/+0
| | | | llvm-svn: 239657
* Replace custom fixed endian to raw_ostream emission with EndianStream.Benjamin Kramer2015-06-041-6/+3
| | | | | | Less code, clearer and more efficient. No functionality change intended. llvm-svn: 239040
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-2/+2
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* MC: Update MCCodeEmitter naming. NFC.Jim Grosbach2015-05-151-2/+2
| | | | | | s/EncodeInstruction/encodeInstruction/ llvm-svn: 237469
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-2/+2
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-2/+2
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-2/+2
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-2/+2
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Remove the use of the subtarget in MCCodeEmitter creation andEric Christopher2015-03-101-1/+0
| | | | | | | update all ports accordingly. Required a couple of small rewrites in handling subtarget features during creation in PPC. llvm-svn: 231861
* Remove createAMDGPUMCCodeEmitter and instead just register the correctEric Christopher2015-03-101-2/+3
| | | | | | | MCCodeEmitter creation routine based on TargetMachine since the only 64-bit R600 gpus are part of the GCN target. llvm-svn: 231856
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-2/+2
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-2/+2
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* Removing LLVM_DELETED_FUNCTION, as MSVC 2012 was the last reason for ↵Aaron Ballman2015-02-151-2/+2
| | | | | | requiring the macro. NFC; LLVM edition. llvm-svn: 229340
* Convert some assert(0) to llvm_unreachable or fold an 'if' condition into ↵Craig Topper2014-06-191-9/+5
| | | | | | the assert. llvm-svn: 211254
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-5/+5
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* Delete MCSubtargetInfo data members from target MCCodeEmitter classesDavid Woodhouse2014-01-281-5/+3
| | | | | | | | The subtarget info is explicitly passed to the EncodeInstruction method and we should use that subtarget info to influence any encoding decisions. llvm-svn: 200350
* Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()David Woodhouse2014-01-281-5/+7
| | | | llvm-svn: 200349
* Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()David Woodhouse2014-01-281-2/+4
| | | | llvm-svn: 200348
* Remove unused stdio.h includesDmitri Gribenko2013-08-181-1/+0
| | | | llvm-svn: 188626
* R600: Use correct encoding for Vertex Fetch instructions on CaymanTom Stellard2013-06-141-1/+3
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184016
* Fix 32 bit build in c++11 mode.Rafael Espindola2013-05-231-1/+1
| | | | | | | | The error was: error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing] MI.getOperand(6).getImm() & 0x1F, llvm-svn: 182584
* s/u_int32_t/uint32_t/Rafael Espindola2013-05-221-2/+2
| | | | llvm-svn: 182444
* Fix the build in c++11 mode.Rafael Espindola2013-05-171-2/+2
| | | | | | | | | | | | The errors were: non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list and non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list llvm-svn: 182168
* R600: Improve texture handlingVincent Lejeune2013-05-171-72/+23
| | | | llvm-svn: 182125
* R600: Fix encoding for R600 family GPUsTom Stellard2013-05-171-0/+7
| | | | | | | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64193 https://bugs.freedesktop.org/show_bug.cgi?id=64257 https://bugs.freedesktop.org/show_bug.cgi?id=64320 NOTE: This is a candidate for the 3.3 branch. llvm-svn: 182113
* R600: Pass MCSubtargetInfo reference to R600CodeEmitterTom Stellard2013-05-171-4/+7
| | | | llvm-svn: 182112
* Remove unused fields and arguments.Rafael Espindola2013-05-131-9/+4
| | | | llvm-svn: 181706
* R600: Remove dead code from the CodeEmitter v2Tom Stellard2013-05-061-397/+59
| | | | | | | | | v2: - Replace switch statement with TSFlags query Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181229
* R600: Stop emitting the instruction type byte before each instructionTom Stellard2013-05-061-33/+2
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181225
* R600: Emit ISA for CALL_FS_* instructionsTom Stellard2013-05-061-1/+0
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181223
* R600: use native for aluVincent Lejeune2013-04-301-2/+5
| | | | llvm-svn: 180761
* R600: Add a Bank Swizzle operandVincent Lejeune2013-04-301-1/+1
| | | | llvm-svn: 180758
* R600: Turn TEX/VTX into native instructionsVincent Lejeune2013-04-301-5/+11
| | | | llvm-svn: 180756
* R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune2013-04-231-4/+0
| | | | llvm-svn: 180124
* R600: Add CF_ENDVincent Lejeune2013-04-231-1/+5
| | | | llvm-svn: 180123
* R600: Export is emitted as a CF_NATIVE instVincent Lejeune2013-04-171-10/+5
| | | | llvm-svn: 179685
* R600: Control Flow support for pre EG genVincent Lejeune2013-04-081-10/+20
| | | | llvm-svn: 179020
* R600: Use a mask for offsets when encoding instructionsVincent Lejeune2013-04-041-2/+5
| | | | llvm-svn: 178763
* R600: Add support for native control flowVincent Lejeune2013-04-011-1/+20
| | | | llvm-svn: 178505
* R600: Emit CF_ALU and use true kcache register.Vincent Lejeune2013-04-011-1/+9
| | | | llvm-svn: 178503
* R600: Emit native instructions for texVincent Lejeune2013-03-311-98/+72
| | | | llvm-svn: 178452
* Use LLVM_DELETED_FUNCTION rather than '// do not implement' comments.David Blaikie2013-02-181-2/+2
| | | | | | | Also removes some redundant DNI comments on function declarations already using the macro. llvm-svn: 175466
* R600: Support for TBOVincent Lejeune2013-02-181-1/+2
| | | | | | | NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175445
* R600: Add support for 128-bit parametersTom Stellard2013-02-131-0/+1
| | | | | NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175096
* R600: rework handling of the constantsTom Stellard2013-01-231-38/+43
| | | | | | | | | | | | | | | | | | | | Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173222
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-2/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* Add R600 backendTom Stellard2012-12-111-0/+575
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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