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path: root/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-642/+0
| | | | llvm-svn: 239657
* Remove a hack that tries to align '*'.Rafael Espindola2015-06-121-1/+1
| | | | | | | | | | | | The alignment is not required, so we can just remove it for now. The old code is a hack as it depends on the buffer management to find the current column. If the alignment is really desirable, the proper way to do it is to pass in a formatted_raw_stream that knows the current column. llvm-svn: 239603
* MC: Add target hook to control symbol quotingMatt Arsenault2015-06-091-1/+1
| | | | llvm-svn: 239370
* R600/SI: Initial support for assembler and inline assemblyTom Stellard2015-04-081-2/+3
| | | | | | | | | | | | | This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
* R600/SI: Don't print offset0/offset1 DS operands when they are 0Tom Stellard2015-04-081-4/+8
| | | | llvm-svn: 234379
* [MCInstPrinter] Enable MCInstPrinter to change its behavior based on theAkira Hatanaka2015-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | per-function subtarget. Currently, code-gen passes the default or generic subtarget to the constructors of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which enables some targets (AArch64, ARM, and X86) to change their instprinter's behavior based on the subtarget feature bits. Since the backend can now use different subtargets for each function, instprinter has to be changed to use the per-function subtarget rather than the default subtarget. This patch takes the first step towards enabling instprinter to change its behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the various print methods table-gen auto-generates. I will follow up with changes to instprinters of AArch64, ARM, and X86. llvm-svn: 233411
* R600/SI: Remove _e32 and _e64 suffixes from mnemonicsTom Stellard2015-03-121-0/+10
| | | | | | | | Instead print them as part of the $dst operand. The AsmMatcher requires the 32-bit and 64-bit encodings have the same mnemonic in order to parse them correctly. llvm-svn: 232105
* R600/SI: Move gds operand to the end of operand listTom Stellard2015-03-091-0/+6
| | | | | | Also print it in the assembly string. llvm-svn: 231684
* R600/SI: Fix mad*k definitionsMatt Arsenault2015-02-211-0/+2
| | | | llvm-svn: 230146
* [cleanup] Re-sort all the #include lines in LLVM usingChandler Carruth2015-01-141-2/+1
| | | | | | | | | | | utils/sort_includes.py. I clearly haven't done this in a while, so more changed than usual. This even uncovered a missing include from the InstrProf library that I've added. No functionality changed here, just mechanical cleanup of the include order. llvm-svn: 225974
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-6/+58
| | | | llvm-svn: 224458
* R600/SI: Change mubuf offsets to print as decimalMatt Arsenault2014-12-031-1/+1
| | | | | | This matches SC's behavior. llvm-svn: 223194
* R600/SI: Change how DS offsets are printedMatt Arsenault2014-10-101-0/+31
| | | | | | | Match SC by using offset/offset0/offset1 and printing in decimal. llvm-svn: 219537
* R600/SI: Fix printing of clamp and omodMatt Arsenault2014-09-301-0/+17
| | | | | | | | No tests for omod since nothing uses it yet, but this should get rid of the remaining annoying trailing zeros after some instructions. llvm-svn: 218692
* R600/SI: Fix hardcoded values for modifiers.Matt Arsenault2014-09-291-3/+5
| | | | | | Move enums to SIDefines.h llvm-svn: 218610
* R600/SI: Fix emitting trailing whitespace after s_waitcntMatt Arsenault2014-09-261-5/+19
| | | | llvm-svn: 218486
* Use llvm_unreachable instead of assert(!)Matt Arsenault2014-09-211-2/+2
| | | | llvm-svn: 218222
* R600/SI: Don't use strings for single charactersMatt Arsenault2014-09-211-18/+18
| | | | llvm-svn: 218221
* R600/SI: Change formatting of printed FP immediatesMatt Arsenault2014-09-171-13/+26
| | | | | | | | | | Only 1 decimal place should be printed for inline immediates. Other constants should be hex constants. Does not include f64 tests because folding those inline immediates currently does not work. llvm-svn: 217964
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+21
| | | | llvm-svn: 217777
* R600/SI: Update MUBUF assembly string to match AMD proprietary compilerTom Stellard2014-08-051-0/+44
| | | | llvm-svn: 214866
* Fix missing words in sentenceMatt Arsenault2014-06-231-3/+3
| | | | llvm-svn: 211511
* Use helper functionMatt Arsenault2014-06-231-7/+2
| | | | llvm-svn: 211510
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-101-0/+12
| | | | llvm-svn: 208479
* R600/SI: Print more immediates in hex formatMatt Arsenault2014-04-151-1/+40
| | | | | | | | | Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. llvm-svn: 206335
* R600/SI: Cleanup parsing of register names.Matt Arsenault2014-04-151-31/+44
| | | | | | Try to figure out the class and number of subregisters. llvm-svn: 206334
* R600/SI: Add intrinsic for S_SENDMSG instructionMichel Danzer2014-01-271-0/+31
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200195
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-121-2/+63
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
* R600: improve dump of S_WAITCNTVincent Lejeune2013-10-131-0/+17
| | | | llvm-svn: 192557
* R600: Bank Swizzle now display SCL equivalentVincent Lejeune2013-06-291-3/+3
| | | | llvm-svn: 185267
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-1/+1
| | | | | | while there. llvm-svn: 182594
* R600: Improve texture handlingVincent Lejeune2013-05-171-0/+45
| | | | llvm-svn: 182125
* R600: prettier dump of clampVincent Lejeune2013-05-171-1/+1
| | | | llvm-svn: 182121
* R600: Improve asmPrint of ALU clauseVincent Lejeune2013-05-021-0/+12
| | | | llvm-svn: 180957
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-021-2/+31
| | | | llvm-svn: 180956
* R600/SI: add all the other missing asm operands v2Christian Konig2013-02-211-0/+4
| | | | | | | | | v2: put implicit parameters in [] Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175754
* R600/SI: Fix int_SI_fs_interp_constantMichel Danzer2013-02-141-0/+15
| | | | | | | | | | | | | | | | The important fix is that the constant interpolation value is stored in the parameter slot P0, which is encoded as 2. In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and add a special operand class for the parameter slots for type checking and pretty printing. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175193
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* R600: rework handling of the constantsTom Stellard2013-01-231-0/+24
| | | | | | | | | | | | | | | | | | | | Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173222
* Add R600 backendTom Stellard2012-12-111-0/+132
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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