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* R600 -> AMDGPU renameTom Stellard2015-06-131-1380/+0
| | | | llvm-svn: 239657
* R600/SI: Add assembler support for FLAT instructionsTom Stellard2015-06-121-0/+65
| | | | | | | | - Add glc, slc, and tfe operands to flat instructions - Add missing flat instructions - Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3. llvm-svn: 239637
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-1/+1
| | | | llvm-svn: 238634
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-1/+1
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-181-1/+1
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-6/+6
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-1/+1
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-1/+1
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* R600/SI: Use a better error message for unsupported instructions in the ↵Tom Stellard2015-04-231-1/+1
| | | | | | assembler llvm-svn: 235627
* R600/SI: Improve AsmParser support for forced e64 encodingTom Stellard2015-04-231-5/+45
| | | | | | | We can now force e64 encoding even when the operands would be legal for e32 encoding. llvm-svn: 235626
* R600/SI: Initial support for assembler and inline assemblyTom Stellard2015-04-081-69/+1025
| | | | | | | | | | | | | This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
* Fix uses of reserved identifiers starting with an underscore followed by an ↵David Blaikie2015-03-161-4/+3
| | | | | | | | | uppercase letter This covers essentially all of llvm's headers and libs. One or two weird cases I wasn't sure were worth/appropriate to fix. llvm-svn: 232394
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-061-0/+1
| | | | | | | | | | | | This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
* Minor cleanup to all the switches after MatchInstructionImpl in all the ↵Craig Topper2015-01-031-16/+15
| | | | | | | | AsmParsers. Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation. llvm-svn: 225114
* R600/SI: Start implementing an assemblerTom Stellard2014-11-141-0/+320
This was done using the Sparc and PowerPC AsmParsers as guides. So far it is very simple and only supports sopp instructions. llvm-svn: 221994
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