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path: root/llvm/lib/Target/R600/AMDILISelDAGToDAG.cpp
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* R600: Rename AMDILISelDAGToDAG.cpp -> AMDGPUISelDAGToDAG.cppTom Stellard2013-07-231-789/+0
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186920
* R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()Tom Stellard2013-07-231-49/+93
| | | | | | | | | | This increases the number of opportunites we have for folding. With the previous implementation we were unable to fold into any instructions other than the first when multiple instructions were selected from a single SDNode. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186919
* R600: Use KCache for kernel argumentsTom Stellard2013-07-231-17/+4
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186918
* R600: Add local memory support via LDSTom Stellard2013-06-281-5/+10
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-251-45/+46
| | | | llvm-svn: 184880
* Access the TargetLoweringInfo from the TargetMachine object instead of ↵Bill Wendling2013-06-191-3/+3
| | | | | | caching it. The TLI may change between functions. No functionality change. llvm-svn: 184360
* Use GetUnderlyingObject instead of custom functionMatt Arsenault2013-06-181-58/+20
| | | | llvm-svn: 184261
* R600: Don't try to fix reg class when copying IMPLICIT_DEF to a registerTom Stellard2013-06-131-1/+2
| | | | | | | | | The test case for this is way too complex to be useful as a lit test, and I was unable to reduce it. https://bugs.freedesktop.org/show_bug.cgi?id=65438 llvm-svn: 183937
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-6/+5
| | | | | | | | This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
* Cast to the proper type.Bill Wendling2013-06-061-1/+1
| | | | llvm-svn: 183365
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-041-45/+141
| | | | llvm-svn: 183278
* R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()Tom Stellard2013-06-031-5/+33
| | | | | | | | | | The CopyToReg nodes will sometimes try to copy a value from a VGPR to an SGPR. This kind of copy is not possible, so we need to detect VGPR->SGPR copies and do something else. The current strategy is to replace these copies with VGPR->VGPR copies and hope that all the users of CopyToReg can accept VGPRs as arguments. llvm-svn: 183132
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-2/+2
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-1/+1
| | | | | | while there. llvm-svn: 182594
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-191-1/+1
| | | | llvm-svn: 179901
* R600/SI: Add support for buffer stores v2Tom Stellard2013-04-051-0/+23
| | | | | | | | v2: - Use the ADDR64 bit Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 178931
* R600: Factorize code handling Const Read Port limitationVincent Lejeune2013-03-141-8/+25
| | | | llvm-svn: 177078
* R600: Turn BUILD_VECTOR into Reg_SequenceVincent Lejeune2013-03-051-0/+29
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 176487
* R600/SI: add post ISel folding for SI v2Christian Konig2013-02-261-0/+1
| | | | | | | | | | Include immediate folding and SGPR limit handling for VOP3 instructions. v2: remove leftover hasExtraSrcRegAllocReq Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176101
* R600/SI: add folding helperChristian Konig2013-02-261-0/+19
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176100
* R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune2013-02-141-0/+2
| | | | | | | | | It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175183
* R600: Do not fold modifier/litterals in vector instVincent Lejeune2013-02-141-2/+5
| | | | | | | | | This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175180
* R600/SI: simplify and fix SMRD encodingTom Stellard2013-02-071-53/+0
| | | | | | | | | | The _SGPR variants where wrong. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174653
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* R600: Fold clamp, neg, absTom Stellard2013-01-311-3/+48
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174099
* R600: Consider bitcast when folding const_address node.Tom Stellard2013-01-311-0/+3
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174098
* R600: rework handling of the constantsTom Stellard2013-01-231-1/+83
| | | | | | | | | | | | | | | | | | | | Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173222
* Add R600 backendTom Stellard2012-12-111-0/+485
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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