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path: root/llvm/lib/Target/R600/AMDGPUMCInstLower.h
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* R600 -> AMDGPU renameTom Stellard2015-06-131-35/+0
| | | | llvm-svn: 239657
* R600/SI: Don't shrink instructions whose e32 encoding doesn't existMarek Olsak2015-01-151-14/+0
| | | | | | | | v2: modify hasVALU32BitEncoding instead v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both hasVALU32BitEncoding and AMDGPUMCInstLower::lower - report an error if a pseudo can't be lowered llvm-svn: 226188
* R600/SI: Add VI instructionsMarek Olsak2014-12-071-1/+2
| | | | llvm-svn: 223603
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Alphabetize forward declarationsMatt Arsenault2014-06-231-2/+2
| | | | llvm-svn: 211509
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-161-1/+15
| | | | | | | | This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. llvm-svn: 209028
* R600: BB operand support for SITom Stellard2012-12-171-1/+4
| | | | | | | | | Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 170342
* Add R600 backendTom Stellard2012-12-111-0/+31
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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