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path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
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* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-13/+16
* R600/SI: Add class intrinsicMatt Arsenault2015-01-061-0/+5
* R600: Remove outdated commentMatt Arsenault2014-12-191-4/+0
* R600/SI: Only form min/max with 1 use.Matt Arsenault2014-12-191-1/+1
* R600: Fix min/max matching problems with unordered comparesMatt Arsenault2014-12-121-42/+43
* Add target hook for whether it is profitable to reduce load widthsMatt Arsenault2014-12-121-0/+23
* R600/SI: Update instruction conversions for VIMarek Olsak2014-12-071-1/+19
* R600/SI: Use ZeroOrNegativeOneBooleanContentMatt Arsenault2014-11-261-0/+3
* R600: Fix assert on copy of an i1 on pre-SIMatt Arsenault2014-11-231-1/+2
* R600: Permute operands when selecting legacy min/maxMatt Arsenault2014-11-151-6/+9
* R600: Fix 64-bit integer divisionTom Stellard2014-11-151-2/+2
* R600: Factor i64 UDIVREM lowering into its own fuctionTom Stellard2014-11-151-0/+81
* R600/SI: Combine min3/max3 instructionsMatt Arsenault2014-11-141-0/+6
* R600/SI: Match integer min / max instructionsMatt Arsenault2014-11-141-21/+69
* R600/SI: Fix fmin_legacy / fmax_legacy matching for SIMatt Arsenault2014-11-131-19/+50
* We can get the TLOF from the TargetMachine - so constructor no longer require...Aditya Nandakumar2014-11-131-1/+1
* R600: Error on initializer for LDS.Matt Arsenault2014-11-131-2/+21
* This patch changes the ownership of TLOF from TargetLoweringBase to TargetMac...Aditya Nandakumar2014-11-131-1/+1
* Add minnum / maxnum codegenMatt Arsenault2014-10-211-0/+2
* R600/SI: Add missing parameter to div_fmas intrinsicMatt Arsenault2014-10-211-0/+2
* R600: Fix nonsensical implementation of computeKnownBits for BFEMatt Arsenault2014-10-161-5/+1
* R600: Remove dead functionMatt Arsenault2014-10-161-12/+0
* R600: Remove unnecessary part of computeKnownBitsForTargetNodeMatt Arsenault2014-10-151-5/+0
* Move variable down to useMatt Arsenault2014-10-151-4/+4
* R600: Fix miscompiles when BFE has multiple usesMatt Arsenault2014-10-151-7/+10
* R600: Use existing variableMatt Arsenault2014-10-151-1/+1
* R600: Remove outdated commentMatt Arsenault2014-10-151-3/+0
* R600/SI: Custom lower f64 -> i64 conversionsMatt Arsenault2014-10-031-0/+53
* R600: Custom lower [s|u]int_to_fp for i64 -> f64Matt Arsenault2014-10-031-2/+43
* R600/SI: Fix ftrunc f64 conformance failures.Matt Arsenault2014-10-031-1/+1
* R600/SI: Add a note about the order of the operands to div_scaleMatt Arsenault2014-09-261-0/+6
* R600: Don't set BypassSlowDiv for 64-bit divisionTom Stellard2014-09-221-3/+0
* R600/SI: Use ISD::MUL instead of ISD::UMULO when lowering divisionTom Stellard2014-09-221-3/+3
* R600: Better fix for bug 20982Matt Arsenault2014-09-191-6/+3
* R600: Bug 20982 - Avoid undefined left shift of negative valueMatt Arsenault2014-09-181-3/+10
* R600: Custom lower fremMatt Arsenault2014-09-101-0/+19
* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-291-0/+1
* name change: isPow2DivCheap -> isPow2SDivCheapSanjay Patel2014-08-211-1/+1
* R600/SI: Use source modifiers for f64 fnegMatt Arsenault2014-08-151-1/+1
* R600/SI: Use source modifier for f64 fabsMatt Arsenault2014-08-151-1/+1
* R600/SI: Add intrinsic for ldexpMatt Arsenault2014-08-151-0/+5
* R600: Use optimized 24bit path in udivremJan Vesely2014-08-121-17/+38
* R600: Remove unused code.Jan Vesely2014-08-121-168/+0
* R600: Use i24 optimized path for SREMJan Vesely2014-08-121-7/+27
* R600: Disable FP exceptions.Matt Arsenault2014-08-091-0/+5
* R600/SI: Avoid generating REGISTER_LOAD instructions.Tom Stellard2014-08-051-1/+2
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+4
* Use the known address space constant rather than checking itMatt Arsenault2014-08-041-1/+1
* Revert "R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp"Tom Stellard2014-08-011-1/+37
* R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cppTom Stellard2014-08-011-37/+1
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