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path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
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* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-191-2/+30
* Use stdint macros for specifying size of constantsMatt Arsenault2014-06-181-2/+3
* R600: Handle fnearbyintMatt Arsenault2014-06-181-0/+12
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-181-1/+1
* R600: Expand vector fceilJan Vesely2014-06-181-0/+1
* Work around ridiculous warning.Matt Arsenault2014-06-181-2/+5
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-181-0/+4
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-181-0/+107
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-181-0/+26
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-171-0/+2
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-0/+1
* SelectionDAG: Expand i64 = FP_TO_SINT i32Tom Stellard2014-06-171-0/+1
* Fix copy paste errorMatt Arsenault2014-06-151-1/+1
* R600: Remove a few more things from AMDILISelLoweringMatt Arsenault2014-06-151-19/+21
* R600: Fix assert on vector sdivMatt Arsenault2014-06-151-4/+4
* R600: Move / cleanup more leftover AMDIL stuff.Matt Arsenault2014-06-151-5/+19
* R600: Move division custom lowering out of AMDILISelLoweringMatt Arsenault2014-06-151-2/+246
* R600: Report that integer division is expensive.Matt Arsenault2014-06-151-0/+7
* R600: Fix asserts related to constant initializersMatt Arsenault2014-06-141-5/+20
* R600: Use address space enum instead of valueMatt Arsenault2014-06-141-6/+7
* R600: Cleanup some old AMDIL stuff.Matt Arsenault2014-06-131-9/+31
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-131-3/+7
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-121-11/+15
* R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault2014-06-111-1/+16
* Try to fix the msvc build.Rafael Espindola2014-06-111-1/+2
* Use cast instead of assert + dyn_castMatt Arsenault2014-06-111-3/+2
* R600: Add helper functions.Matt Arsenault2014-06-111-0/+19
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-101-2/+6
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-101-1/+11
* R600: Handle fcopysignMatt Arsenault2014-06-101-0/+7
* R600: Fix selection failure for vector bswapMatt Arsenault2014-06-091-0/+1
* R600: Set all float vector expands in the same placeMatt Arsenault2014-06-011-5/+2
* R600: Try to convert BFE back to standard bit ops when possible.Matt Arsenault2014-05-221-0/+21
* R600: Add dag combine for BFEMatt Arsenault2014-05-221-0/+74
* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-221-0/+25
* R600: Implement computeMaskedBitsForTargetNode for BFEMatt Arsenault2014-05-221-1/+29
* R600: Add intrinsics for mad24Matt Arsenault2014-05-221-0/+10
* R600: Add comment describing problems with LowerConstantInitializerMatt Arsenault2014-05-211-0/+10
* R600: Partially fix constant initializers for structs and vectors.Matt Arsenault2014-05-211-6/+33
* Use cast<> instead of unchecked dyn_castMatt Arsenault2014-05-211-1/+1
* Use range forMatt Arsenault2014-05-151-6/+2
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-141-14/+14
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-121-0/+8
* Fix return before elseMatt Arsenault2014-05-111-18/+18
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+2
* R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard2014-05-091-9/+13
* R600: Promote f64 vector load/stores to i64 for consistencyMatt Arsenault2014-05-081-0/+6
* R600: Expand i64 ISD:SUBTom Stellard2014-05-051-0/+1
* R600: Expand vector sin and cos.Tom Stellard2014-05-021-0/+2
* R600: Expand TruncStore i64 -> {i16,i8}Tom Stellard2014-05-021-0/+2
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