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* Mark INSERT_VECTOR_ELT as expandChris Lattner2006-03-311-0/+1
| | | | llvm-svn: 27276
* Add the rest of the vmul instructions and the vmulsum* instructions.Chris Lattner2006-03-301-1/+15
| | | | llvm-svn: 27268
* Use a new tblgen feature to significantly shrinkify instruction definitions thatChris Lattner2006-03-301-108/+46
| | | | | | directly correspond to intrinsics. llvm-svn: 27266
* Add a bunch of new instructions for intrinsics.Chris Lattner2006-03-301-6/+87
| | | | llvm-svn: 27265
* add a noteChris Lattner2006-03-291-0/+4
| | | | llvm-svn: 27243
* add a noteChris Lattner2006-03-281-0/+10
| | | | llvm-svn: 27227
* Expose base register for DwarfWriter. Refactor code accordingly.Jim Laskey2006-03-282-11/+4
| | | | llvm-svn: 27225
* Fix a couple typosNate Begeman2006-03-281-2/+2
| | | | llvm-svn: 27216
* Add a few more altivec intrinsicsNate Begeman2006-03-283-6/+28
| | | | llvm-svn: 27215
* implement a bunch more intrinsics.Chris Lattner2006-03-282-23/+108
| | | | llvm-svn: 27209
* Use normal lvx for scalar_to_vector instead of lve*x. They do the exactChris Lattner2006-03-284-20/+5
| | | | | | same thing and we have a dag node for the former. llvm-svn: 27205
* Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum ↵Chris Lattner2006-03-282-11/+11
| | | | | | value. Split them into separate enums. llvm-svn: 27201
* Translate llvm target registers to dwarf register numbers properly.Jim Laskey2006-03-271-1/+1
| | | | llvm-svn: 27180
* Add a bunch of notes from my journey thus far.Chris Lattner2006-03-271-9/+103
| | | | llvm-svn: 27170
* Split out altivec notes into their own READMEChris Lattner2006-03-272-52/+56
| | | | llvm-svn: 27168
* Fix the JIT encoding of VSELChris Lattner2006-03-272-4/+24
| | | | llvm-svn: 27160
* Fix the JIT encoding of VSPLTI*Chris Lattner2006-03-272-9/+24
| | | | llvm-svn: 27159
* SelectionDAGISel can now natively handle Switch instructions, in the sameNate Begeman2006-03-271-1/+9
| | | | | | | | | | | | | | manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary search tree of basic blocks. The new approach has several advantages: it is faster, it generates significantly smaller code in many cases, and it paves the way for implementing dense switch tables as a jump table by handling switches directly in the instruction selector. This functionality is currently only enabled on x86, but should be safe for every target. In anticipation of making it the default, the cfg is now properly updated in the x86, ppc, and sparc select lowering code. llvm-svn: 27156
* add vselChris Lattner2006-03-261-0/+4
| | | | llvm-svn: 27153
* Codegen vector predicate compares.Chris Lattner2006-03-265-15/+139
| | | | llvm-svn: 27151
* Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros insteadEvan Cheng2006-03-263-34/+6
| | | | llvm-svn: 27149
* Add all of the altivec comparison instructions. Add patterns for theChris Lattner2006-03-262-5/+108
| | | | | | non-predicate altivec compare intrinsics. llvm-svn: 27143
* Add and 8/16-bit adds, add all integer subtracts, add saturating subtractChris Lattner2006-03-261-3/+53
| | | | | | intrinsics. llvm-svn: 27142
* implement the vsldoi intrinsic.Chris Lattner2006-03-262-4/+26
| | | | llvm-svn: 27139
* fix the pattern for vandc, it's NOT vnandChris Lattner2006-03-251-3/+3
| | | | llvm-svn: 27136
* add patterns for VANDC/VNOR, implementingChris Lattner2006-03-251-3/+8
| | | | | | CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC llvm-svn: 27135
* Add some logical operationsChris Lattner2006-03-251-3/+19
| | | | llvm-svn: 27127
* implement a bunch of intrinsicsChris Lattner2006-03-251-3/+34
| | | | llvm-svn: 27118
* Move all Altivec stuff out into a new PPCInstrAltivec.td file.Chris Lattner2006-03-252-239/+298
| | | | | | | Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and zero vector support. llvm-svn: 27117
* Add some basic patterns for other datatypesChris Lattner2006-03-252-10/+12
| | | | llvm-svn: 27116
* add all supported formats to the vector register fileChris Lattner2006-03-251-1/+1
| | | | llvm-svn: 27115
* Add support for __builtin_altivec_vnmsubfp /vmaddfpChris Lattner2006-03-251-0/+5
| | | | llvm-svn: 27112
* #include Intrinsics.h into all dag iselsChris Lattner2006-03-252-0/+8
| | | | llvm-svn: 27109
* Codegen things like:Chris Lattner2006-03-254-2/+123
| | | | | | | | | | | | | | | | | <int -1, int -1, int -1, int -1> and <int 65537, int 65537, int 65537, int 65537> Using things like: vspltisb v0, -1 and: vspltish v0, 1 instead of using constant pool loads. This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}. llvm-svn: 27106
* Add dwarf register numbering to register data.Jim Laskey2006-03-241-71/+140
| | | | llvm-svn: 27081
* add another noteChris Lattner2006-03-241-0/+15
| | | | llvm-svn: 27077
* Fix a bad JIT encoding of VPERM. Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??Chris Lattner2006-03-241-2/+2
| | | | llvm-svn: 27069
* Like the comment says, prefer to use the implicit add done by [r+r] addressingChris Lattner2006-03-241-4/+14
| | | | | | | modes than emitting an explicit add and using a base of r0. This implements Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll llvm-svn: 27068
* Disable the i32->float G5 optimization. It is unsafe, as documented in theChris Lattner2006-03-241-1/+7
| | | | | | | | comment. This fixes 177.mesa, and McCat/09-vor with the td scheduler. llvm-svn: 27060
* add support for using vxor to build zero vectors. This implementsChris Lattner2006-03-243-4/+44
| | | | | | Regression/CodeGen/PowerPC/vec_zero.ll llvm-svn: 27059
* Gabor points out that we can't spell. :)Chris Lattner2006-03-241-1/+1
| | | | llvm-svn: 27049
* add a noteChris Lattner2006-03-231-0/+10
| | | | llvm-svn: 27000
* Add PPC vector bit-convert supportChris Lattner2006-03-231-0/+3
| | | | llvm-svn: 26995
* Add support to locate local variables in frames (early version.)Jim Laskey2006-03-232-0/+15
| | | | llvm-svn: 26994
* Change interface to DwarfWriter.Jim Laskey2006-03-231-4/+4
| | | | llvm-svn: 26991
* Eliminate IntrinsicLowering from TargetMachine.Chris Lattner2006-03-232-8/+3
| | | | | | Make the CBE and V9 backends create their own, since they're the only ones that use it. llvm-svn: 26974
* This has been implemented. Tweak it into another noteChris Lattner2006-03-221-23/+9
| | | | llvm-svn: 26944
* When possible, custom lower 32-bit SINT_TO_FP to this:Chris Lattner2006-03-225-32/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | _foo2: extsw r2, r3 std r2, -8(r1) lfd f0, -8(r1) fcfid f0, f0 frsp f1, f0 blr instead of this: _foo2: lis r2, ha16(LCPI2_0) lis r4, 17200 xoris r3, r3, 32768 stw r3, -4(r1) stw r4, -8(r1) lfs f0, lo16(LCPI2_0)(r2) lfd f1, -8(r1) fsub f0, f1, f0 frsp f1, f0 blr This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s with llcbeta (16.7% and 38.1% respectively). llvm-svn: 26943
* Add support for "ri" addressing modes where the immediate is a 14-bit fieldChris Lattner2006-03-222-0/+95
| | | | | | | which is shifted left two bits before use. Instructions like STD use this addressing mode. llvm-svn: 26942
* Fix the JIT encoding of the VAForm_1 instructions, including vmaddfpChris Lattner2006-03-222-9/+8
| | | | llvm-svn: 26935
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