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authorChris Lattner <sabre@nondot.org>2006-03-25 08:01:02 +0000
committerChris Lattner <sabre@nondot.org>2006-03-25 08:01:02 +0000
commit1b4bb22f8a96845aea9734570eb354559e4064be (patch)
tree9d3c8ffd82949e2db14749e676c9ef98f05e2abf /llvm/lib/Target/PowerPC
parent2a85fa1f792f1a58da30118217e43dd782661963 (diff)
downloadbcm5719-llvm-1b4bb22f8a96845aea9734570eb354559e4064be.tar.gz
bcm5719-llvm-1b4bb22f8a96845aea9734570eb354559e4064be.zip
implement a bunch of intrinsics
llvm-svn: 27118
Diffstat (limited to 'llvm/lib/Target/PowerPC')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrAltivec.td37
1 files changed, 34 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index 4e34d4ef6a8..9338e5476cf 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -124,18 +124,49 @@ def VPERM : VAForm_1<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
// VX-Form instructions. AltiVec arithmetic ops.
+def VADDCUW : VXForm_1<384, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vaddcuw $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vaddcuw VRRC:$vA, VRRC:$vB))]>;
def VADDFP : VXForm_1<10, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vaddfp $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>;
+def VADDSBS : VXForm_1<768, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vaddsbs $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vaddsbs VRRC:$vA, VRRC:$vB))]>;
+def VADDSHS : VXForm_1<832, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vaddshs $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vaddshs VRRC:$vA, VRRC:$vB))]>;
+def VADDSWS : VXForm_1<896, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vaddsws $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vaddsws VRRC:$vA, VRRC:$vB))]>;
+def VADDUBS : VXForm_1<512, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vaddubs $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vaddubs VRRC:$vA, VRRC:$vB))]>;
+def VADDUHS : VXForm_1<576, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vadduhs $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vadduhs VRRC:$vA, VRRC:$vB))]>;
def VADDUWM : VXForm_1<128, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vadduwm $vD, $vA, $vB", VecGeneral,
[(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>;
+def VADDUWS : VXForm_1<640, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vadduws $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vadduws VRRC:$vA, VRRC:$vB))]>;
+
def VCFSX : VXForm_1<842, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vcfsx $vD, $vB, $UIMM", VecFP,
- []>;
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>;
def VCFUX : VXForm_1<778, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vcfux $vD, $vB, $UIMM", VecFP,
- []>;
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>;
def VCTSXS : VXForm_1<970, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vctsxs $vD, $vB, $UIMM", VecFP,
[]>;
@@ -171,7 +202,7 @@ def VRFIZ : VXForm_2<586, (ops VRRC:$vD, VRRC:$vB),
[]>;
def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
"vrsqrtefp $vD, $vB", VecFP,
- []>;
+ [(set VRRC:$vD,(int_ppc_altivec_vrsqrtefp VRRC:$vB))]>;
def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vsubfp $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
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