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* Change codegen for setcc to read the bit directly out of the conditionNate Begeman2005-04-183-45/+36
| | | | | | | | register. Added support in the .td file for the g5-specific variant of cr -> gpr moves that executes faster, but we currently don't generate it. llvm-svn: 21314
* Handle ExternalSymbol operands in the PPC JITChris Lattner2005-04-181-9/+13
| | | | llvm-svn: 21312
* Make pattern isel default for ppcNate Begeman2005-04-153-11/+24
| | | | | | | | | | Add new ppc beta option related to using condition registers Make pattern isel control flag (-enable-pattern-isel) global and tristate 0 == off 1 == on 2 == target default llvm-svn: 21309
* Implement multi-way branches through logical ops on condition registers.Nate Begeman2005-04-142-3/+69
| | | | | | | | This can generate considerably shorter code, reducing the size of crafty by almost 1%. Also fix the printing of mcrf. The code is currently disabled until it gets a bit more testing, but should work as-is. llvm-svn: 21298
* Add the necessary support to codegen condition register logical ops withNate Begeman2005-04-144-17/+72
| | | | | | | register allocated condition registers. Make sure that the printed output is gas compatible. llvm-svn: 21295
* Start allocating condition registers. Almost all explicit uses of CR0 areNate Begeman2005-04-131-23/+26
| | | | | | | now gone. Next step is to get rid of the remaining ones and then start allocating bools to CRs where appropriate. llvm-svn: 21294
* Implement the fold shift X, zext(Y) -> shift X, Y at the target level,Nate Begeman2005-04-131-6/+22
| | | | | | where it is safe to do so. llvm-svn: 21293
* Disbale the broken fold of shift + sz[ext] for nowNate Begeman2005-04-131-19/+0
| | | | | | | | Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc always produces zero or one. llvm-svn: 21291
* remove one more occurance of this that snuck inChris Lattner2005-04-131-1/+1
| | | | llvm-svn: 21271
* Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emitChris Lattner2005-04-132-25/+0
| | | | | | | andi instructions instead of rlwinm instructions for zero extend, but they seem like they would take the same time. llvm-svn: 21268
* Fold shift by size larger than type size to undefNate Begeman2005-04-121-1/+0
| | | | | | Make llvm undef values generate ISD::UNDEF nodes llvm-svn: 21261
* Implement setcc op, -1 sequencesNate Begeman2005-04-121-22/+41
| | | | | | | Remove dead setcc op, 0 sequences Coming later: generalization of op, imm llvm-svn: 21260
* Initial support for allocation condition registersNate Begeman2005-04-125-13/+67
| | | | llvm-svn: 21246
* Implement bitfield clearsNate Begeman2005-04-122-11/+35
| | | | | | Implement divide by negative power of two llvm-svn: 21240
* Update PPC readme. Remove things that are done or aren't ppc specificNate Begeman2005-04-111-6/+2
| | | | llvm-svn: 21232
* ORo sets CR0Chris Lattner2005-04-111-0/+1
| | | | llvm-svn: 21227
* Revert the previous patch, which I didn't mean to check in.Chris Lattner2005-04-112-37/+26
| | | | llvm-svn: 21226
* Fix a minor bug (ORo didn't mark that it set CR0).Chris Lattner2005-04-112-26/+37
| | | | | | | | | | | | | | | | | | | | Refactor how . instructions are handled. In particular, instead of passing the RC flag all the way up the inheritance hierarchy, just make a new tblgen class 'DOT' which can be added to an instruction definition. For example, instead of this: -def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), -let Defs = [CR0] in -def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), - "and. $rA, $rS, $rB">; We now have this: +def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), "and $rA, $rS, $rB">; llvm-svn: 21225
* Add recording variants of ISD::AND and ISD::OR. This kills almost 1000Nate Begeman2005-04-112-10/+48
| | | | | | (1.5%) instructions in 186.crafty llvm-svn: 21222
* Fix another fixme: factor out the constant fp generation code.Nate Begeman2005-04-101-17/+2
| | | | llvm-svn: 21207
* Fix 64 bit argument loading that straddles the args in regs / args on stackNate Begeman2005-04-101-7/+15
| | | | | | boundary. llvm-svn: 21206
* Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do notNate Begeman2005-04-101-4/+0
| | | | | | have to inform the register allocator it might be stepped on. llvm-svn: 21202
* Make sure that BRCOND branches can be converted into long branches too.Nate Begeman2005-04-102-2/+4
| | | | llvm-svn: 21198
* Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.Nate Begeman2005-04-101-1/+2
| | | | llvm-svn: 21197
* rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be moreChris Lattner2005-04-101-21/+21
| | | | | | | | | correct. Remove the EmitComparison retvalue, as it is always the first arg. Fix a place where we incorrectly passed in the setcc opcode instead of the setcc number, causing us to miscompile crafty. Crafty now works! llvm-svn: 21195
* fix ISD::BRCONDTWOWAY codegen to not deference the end() iteratorNate Begeman2005-04-091-1/+1
| | | | llvm-svn: 21193
* Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.Chris Lattner2005-04-091-0/+16
| | | | | | | | This caused the "use before a def" assertion on some programs. With this patch, 254.gap now passes with the PPC backend. llvm-svn: 21191
* do not set the root to null if an argument is deadChris Lattner2005-04-091-1/+2
| | | | llvm-svn: 21188
* Add rlwnm instruction for variable rotateNate Begeman2005-04-092-29/+79
| | | | | | | | Generate rotate left/right immediate Generate code for brcondtwoway Use new livein/liveout functionality llvm-svn: 21187
* Fix a crash on 173.applu by asking for a constant bigger than 32-bits.Chris Lattner2005-04-091-1/+1
| | | | llvm-svn: 21185
* Switch this instruction selector over to using liveins and liveouts, eliminatingChris Lattner2005-04-091-8/+26
| | | | | | implicit defs on entry to the function. yaay :) llvm-svn: 21184
* Optimize FSEL a bit for fneg arguments. This fixes the recently added testNate Begeman2005-04-091-11/+12
| | | | | | | | | | | | | | | | | | | | case so that we emit _test_fneg_sel: .LBB_test_fneg_sel_0: ; fsel f1, f1, f3, f2 blr instead of: _test_fneg_sel: .LBB_test_fneg_sel_0: ; fneg f0, f1 fneg f0, f0 fsel f1, f0, f3, f2 blr llvm-svn: 21177
* This target does not yet support ISD::BRCONDTWOWAYChris Lattner2005-04-092-0/+2
| | | | llvm-svn: 21163
* 64b: Expand S/UREMNate Begeman2005-04-092-7/+31
| | | | | | | | | 32b: No longer pattern match fneg(fsub(fmul)) as fnmsub Pattern match fsub a, mul(b, c) as fnmsub Pattern match fadd a, mul(b, c) as fmadd Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8% llvm-svn: 21161
* Fix 64b shiftsNate Begeman2005-04-081-26/+13
| | | | llvm-svn: 21159
* Match Mac OS X 64 bit calling conventionsNate Begeman2005-04-081-116/+46
| | | | llvm-svn: 21157
* Optimized code sequences for setcc reg, 0Nate Begeman2005-04-071-4/+77
| | | | | | Optimized code sequence for (a < 0) ? b : 0 llvm-svn: 21150
* PowerPC zero extends setcc resultsChris Lattner2005-04-071-0/+1
| | | | llvm-svn: 21147
* Pattern match bitfield insert, which helps shift long by immediate, amongNate Begeman2005-04-061-15/+152
| | | | | | other things. llvm-svn: 21127
* Fix some shift bugsNate Begeman2005-04-061-3/+12
| | | | llvm-svn: 21126
* Fixed version of optimized integer divide is now fixed. Calculate theNate Begeman2005-04-061-13/+9
| | | | | | | quotient, not the remainder. Also, make sure to remove the old div operand from the ExprMap and let SelectExpr insert the new one. llvm-svn: 21111
* Turn off the div -> mul optimization until it works correctly 100% of theNate Begeman2005-04-061-5/+5
| | | | | | time. llvm-svn: 21105
* Add support for MULHS and MULHU nodesNate Begeman2005-04-063-21/+194
| | | | | | | | Have LegalizeDAG handle SREM and UREM for us Codegen SDIV and UDIV by constant as a multiply by magic constant instead of integer divide, which is very slow. llvm-svn: 21104
* Behold, rlwinm with certain immediate arguments is printed as the much moreNate Begeman2005-04-051-0/+22
| | | | | | readable slwi or srwi (shift left/right word immediate). llvm-svn: 21099
* Fix cut & paste errors (32->64), and codegen float->int more optimally.Nate Begeman2005-04-051-68/+8
| | | | llvm-svn: 21098
* Remove 64 bit simple ISel, it never worked correctlyNate Begeman2005-04-054-2948/+1769
| | | | | | Add initial (buggy) implementation of 64 bit pattern ISel llvm-svn: 21096
* Back out the previous change to SelectBranchCC, since there are cases itNate Begeman2005-04-051-4/+11
| | | | | | could miscompile. A correct solution will be found in the near future. llvm-svn: 21095
* Rename canUseAsImmediateForOpcode to getImmediateForOpcode to betterNate Begeman2005-04-052-21/+27
| | | | | | | | | indicate that it is not a boolean function. Properly emit the pseudo instruction for conditional branch, so that we can fix up conditional branches whose displacements are too large. Reserve the right amount of opcode space for said pseudo instructions. llvm-svn: 21094
* Implement SDIV by power of 2 as srawi/addze rather than load imm, divwNate Begeman2005-04-051-0/+24
| | | | llvm-svn: 21091
* Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-subNate Begeman2005-04-041-4/+56
| | | | llvm-svn: 21090
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