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authorNate Begeman <natebegeman@mac.com>2005-04-06 06:44:57 +0000
committerNate Begeman <natebegeman@mac.com>2005-04-06 06:44:57 +0000
commit39ef2f1d43d3a0019c10e86e8f2dfb622aaea276 (patch)
treecb7d296c7c739618ce379da0d7ca2c19b38c4e51 /llvm/lib/Target/PowerPC
parentc0e9adf3cc953d1f353cef66d6e9c994437f296b (diff)
downloadbcm5719-llvm-39ef2f1d43d3a0019c10e86e8f2dfb622aaea276.tar.gz
bcm5719-llvm-39ef2f1d43d3a0019c10e86e8f2dfb622aaea276.zip
Fixed version of optimized integer divide is now fixed. Calculate the
quotient, not the remainder. Also, make sure to remove the old div operand from the ExprMap and let SelectExpr insert the new one. llvm-svn: 21111
Diffstat (limited to 'llvm/lib/Target/PowerPC')
-rw-r--r--llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp22
1 files changed, 9 insertions, 13 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
index 465a9bccf1d..3ece1b29f9b 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -551,7 +551,7 @@ static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
if (v <= -2 || v >= 2) { return 4; }
break;
case ISD::UDIV:
- if (v != 0) { return 4; }
+ if (v > 1) { return 4; }
break;
}
return 0;
@@ -711,10 +711,7 @@ SDOperand ISel::BuildSDIVSequence(SDOperand N) {
// Extract the sign bit and add it to the quotient
SDOperand T =
ISelDAG->getNode(ISD::SRL, MVT::i32, Q, ISelDAG->getConstant(31, MVT::i32));
- Q = ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
- // Compute the remainder
- T = ISelDAG->getNode(ISD::MUL, MVT::i32, Q, N.getOperand(1));
- return ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), T);
+ return ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
}
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
@@ -739,9 +736,7 @@ SDOperand ISel::BuildUDIVSequence(SDOperand N) {
Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
ISelDAG->getConstant(magics.s-1, MVT::i32));
}
- // Compute the remainder
- SDOperand T = ISelDAG->getNode(ISD::MUL, MVT::i32, Q, N.getOperand(1));
- return ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), T);
+ return Q;
}
/// getGlobalBaseReg - Output the instructions required to put the
@@ -1601,11 +1596,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
return Result;
// If this is a divide by constant, we can emit code using some magic
// constants to implement it as a multiply instead.
- //case 4:
- // if (opcode == ISD::SDIV)
- // return SelectExpr(BuildSDIVSequence(N));
- // else
- // return SelectExpr(BuildUDIVSequence(N));
+ case 4:
+ ExprMap.erase(N);
+ if (opcode == ISD::SDIV)
+ return SelectExpr(BuildSDIVSequence(N));
+ else
+ return SelectExpr(BuildUDIVSequence(N));
}
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
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