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| author | Chris Lattner <sabre@nondot.org> | 2005-04-13 02:40:26 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-04-13 02:40:26 +0000 |
| commit | 83075510ee730ab24331186d1df878c712f75155 (patch) | |
| tree | 1a2305d6ff58ce84f16c2608f7045a9fb58e2fbe /llvm/lib/Target/PowerPC | |
| parent | 248fe6bda27adeb0aa0e5cb18a26ccc7b08a2087 (diff) | |
| download | bcm5719-llvm-83075510ee730ab24331186d1df878c712f75155.tar.gz bcm5719-llvm-83075510ee730ab24331186d1df878c712f75155.zip | |
Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
llvm-svn: 21268
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp | 12 |
2 files changed, 0 insertions, 25 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp index a2b1e739bdc..1e4b88f5b49 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -1636,19 +1636,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { } return Result; - case ISD::ZERO_EXTEND_INREG: - Tmp1 = SelectExpr(N.getOperand(0)); - switch(cast<MVTSDNode>(Node)->getExtraValueType()) { - default: Node->dump(); assert(0 && "Unhandled ZERO_EXTEND type"); break; - case MVT::i16: Tmp2 = 16; break; - case MVT::i8: Tmp2 = 24; break; - case MVT::i1: Tmp2 = 31; break; - } - Opc = Recording ? PPC::RLWINMo : PPC::RLWINM; - RecordSuccess = true; - BuildMI(BB, Opc, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2).addImm(31); - return Result; - case ISD::CopyFromReg: if (Result == 1) Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); diff --git a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp index 0d706f80f8f..5604a9e8e54 100644 --- a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp @@ -1154,18 +1154,6 @@ unsigned ISel::SelectExpr(SDOperand N) { } return Result; - case ISD::ZERO_EXTEND_INREG: - Tmp1 = SelectExpr(N.getOperand(0)); - switch(cast<MVTSDNode>(Node)->getExtraValueType()) { - default: Node->dump(); assert(0 && "Unhandled ZERO_EXTEND type"); break; - case MVT::i16: Tmp2 = 16; break; - case MVT::i8: Tmp2 = 24; break; - case MVT::i1: Tmp2 = 31; break; - } - BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2) - .addImm(31); - return Result; - case ISD::CopyFromReg: if (Result == 1) Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); |

