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path: root/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-261-1/+1
| | | | | | | The hasFnAttr method has been replaced by querying the Attributes explicitly. No intended functionality change. llvm-svn: 164725
* Change unsigned to uint32_t to match base class declaration and other targets.Craig Topper2012-09-161-1/+1
| | | | llvm-svn: 164001
* This patch corrects logic in PPCFrameLowering for save and restore of ↵Roman Divacky2012-09-121-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | nonvolatile condition register fields across calls under the SVR4 ABIs. * With the 64-bit ABI, the save location is at a fixed offset of 8 from the stack pointer. The frame pointer cannot be used to access this portion of the stack frame since the distance from the frame pointer may change with alloca calls. * With the 32-bit ABI, the save location is just below the general register save area, and is accessed via the frame pointer like the rest of the save areas. This is an optional slot, so it must only be created if any of CR2, CR3, and CR4 were modified. * For both ABIs, save/restore logic is generated only if one of the nonvolatile CR fields were modified. I also took this opportunity to clean up an extra FIXME in PPCFrameLowering.h. Save area offsets for 32-bit GPRs are meaningless for the 64-bit ABI, so I removed them for correctness and efficiency. Fixes PR13708 and partially also PR13623. It lets us enable exception handling on PPC64. Patch by William J. Schmidt! llvm-svn: 163713
* Mark most PPC register classes to avoid write-after-write.Hal Finkel2012-06-191-0/+14
| | | | | | | | | | | | | | | | | | | | | | | For processors with the G5-like instruction-grouping scheme, this helps avoid early group termination due to a write-after-write dependency within the group. It should also help on pipelined embedded cores. On POWER7, over the test suite, this gives an average 0.5% speedup. The largest speedups are: SingleSource/Benchmarks/Stanford/Quicksort - 33% MultiSource/Applications/d/make_dparser - 21% MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12% MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12% Largest slowdowns: SingleSource/Benchmarks/Stanford/Bubblesort - 23% MultiSource/Benchmarks/Prolangs-C++/city/city - 21% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16% MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13% llvm-svn: 158719
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-191-6/+6
| | | | | | PPC will now generate STWUX and friends. llvm-svn: 158698
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+2
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. llvm-svn: 155395
* PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large ↵Hal Finkel2012-03-221-1/+2
| | | | | | | | offsets. Fixes PR12203. I don't have a small test case yet, but I'll try to construct one. llvm-svn: 153240
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Convert PowerPC to register mask operands.Roman Divacky2012-03-061-94/+10
| | | | llvm-svn: 152122
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-5/+5
| | | | | | size of static data. llvm-svn: 151996
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Cleanup PPC RLWINM8 vs RLWINMHal Finkel2012-01-161-1/+1
| | | | | | No test case: output assembly will be identical. llvm-svn: 148261
* Cleanup stack/frame register define/kill states. This fixes two bugs:Hal Finkel2011-12-301-9/+9
| | | | | | | | 1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test). 2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this. llvm-svn: 147359
* Make CR spill and restore use a reserved register. These operations cannot ↵Hal Finkel2011-12-101-10/+18
| | | | | | use the register scavenger because the scavenger can only scavenge one register and frame-index elimination may have already grabbed it. llvm-svn: 146318
* make CR spill and restore 64-bit clean (no functional change), and fix some ↵Hal Finkel2011-12-071-3/+3
| | | | | | other problems found with -verify-machineinstrs llvm-svn: 146024
* make base register selection used in eliminateFrameIndex 64-bit cleanHal Finkel2011-12-071-8/+13
| | | | llvm-svn: 146023
* add RESTORE_CR and support CR unspillsHal Finkel2011-12-061-4/+45
| | | | llvm-svn: 145961
* remove old FIXMEHal Finkel2011-12-061-1/+0
| | | | llvm-svn: 145960
* enable PPC register scavenging by default (update tests and remove some FIXMEs)Hal Finkel2011-12-051-11/+7
| | | | llvm-svn: 145819
* don't include CR bit subregs in callee-saved listHal Finkel2011-12-051-16/+0
| | | | llvm-svn: 145818
* add register pressure for CR regsHal Finkel2011-12-051-0/+2
| | | | llvm-svn: 145816
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-1/+2
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* add basic PPC register-pressure feedback; adjust the vaarg test to match the ↵Hal Finkel2011-11-221-0/+21
| | | | | | new register-allocation pattern llvm-svn: 145065
* Refactor PPC target to separate MC routines from Target routines.Evan Cheng2011-07-251-44/+1
| | | | llvm-svn: 135942
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-181-1/+0
| | | | | | better location welcome). llvm-svn: 135438
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-29/+4
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-1/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134027
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+3
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-241-3/+4
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Fix a few places where 32bit instructions/registerset were used on PPC64.Roman Divacky2011-06-171-1/+2
| | | | llvm-svn: 133260
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-301-0/+8
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Split ppc dwarf regnums into ppc64 and ppc32 flavours.Rafael Espindola2011-05-301-1/+12
| | | | llvm-svn: 132315
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-7/+7
| | | | | | and fixes here and there. llvm-svn: 123170
* Restore the behavior of frame lowering before my refactoring.Anton Korobeynikov2010-12-181-2/+3
| | | | | | | | It turns out that ppc backend has really weird interdependencies over different hooks and all stuff is fragile wrt small changes. This should fix PR8749 llvm-svn: 122155
* Move more PEI-related hooks to TFIAnton Korobeynikov2010-11-271-274/+8
| | | | llvm-svn: 120229
* Move getInitialFrameState() to TargetFrameInfoAnton Korobeynikov2010-11-181-8/+0
| | | | llvm-svn: 119754
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-32/+20
| | | | llvm-svn: 119740
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-151-647/+1
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-261-8/+6
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* PPC doesn't supported VLA with large alignment. This wasDale Johannesen2010-07-301-2/+2
| | | | | | | | formerly rejected by the FE, so asserted in the BE; now the FE only warns, so we treat it as a legitimate fatal error in PPC BE. This means the test for the feature won't pass, so it's xfail'd. llvm-svn: 109892
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-2/+2
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-031-4/+2
| | | | | | slots so it's always false. llvm-svn: 107550
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-14/+12
| | | | llvm-svn: 105344
* cleanupRafael Espindola2010-06-021-134/+0
| | | | llvm-svn: 105322
* The PPC MFCR instruction implicitly uses all 8 of the CRDale Johannesen2010-05-201-8/+4
| | | | | | | | | | | | | | registers. Currently it is not so marked, which leads to VCMPEQ instructions that feed into it getting deleted. If it is so marked, local RA complains about this sequence: vreg = MCRF CR0 MFCR <kill of whatever preg got assigned to vreg> All current uses of this instruction are only interested in one of the 8 CR registers, so redefine MFCR to be a normal unary instruction with a CR input (which is emitted only as a comment). That avoids all problems. 7739628. llvm-svn: 104238
* Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe whatBill Wendling2010-05-141-1/+1
| | | | | | | | | the variable actually tracks. N.B., several back-ends are using "HasCalls" as being synonymous for something that adjusts the stack. This isn't 100% correct and should be looked into. llvm-svn: 103802
* Make naked functions work on PPC.Dale Johannesen2010-04-291-1/+7
| | | | llvm-svn: 102657
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