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path: root/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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* don't include CR bit subregs in callee-saved listHal Finkel2011-12-051-16/+0
| | | | llvm-svn: 145818
* add register pressure for CR regsHal Finkel2011-12-051-0/+2
| | | | llvm-svn: 145816
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-1/+2
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* add basic PPC register-pressure feedback; adjust the vaarg test to match the ↵Hal Finkel2011-11-221-0/+21
| | | | | | new register-allocation pattern llvm-svn: 145065
* Refactor PPC target to separate MC routines from Target routines.Evan Cheng2011-07-251-44/+1
| | | | llvm-svn: 135942
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-181-1/+0
| | | | | | better location welcome). llvm-svn: 135438
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-29/+4
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-1/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134027
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+3
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-241-3/+4
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Fix a few places where 32bit instructions/registerset were used on PPC64.Roman Divacky2011-06-171-1/+2
| | | | llvm-svn: 133260
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-301-0/+8
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Split ppc dwarf regnums into ppc64 and ppc32 flavours.Rafael Espindola2011-05-301-1/+12
| | | | llvm-svn: 132315
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-7/+7
| | | | | | and fixes here and there. llvm-svn: 123170
* Restore the behavior of frame lowering before my refactoring.Anton Korobeynikov2010-12-181-2/+3
| | | | | | | | It turns out that ppc backend has really weird interdependencies over different hooks and all stuff is fragile wrt small changes. This should fix PR8749 llvm-svn: 122155
* Move more PEI-related hooks to TFIAnton Korobeynikov2010-11-271-274/+8
| | | | llvm-svn: 120229
* Move getInitialFrameState() to TargetFrameInfoAnton Korobeynikov2010-11-181-8/+0
| | | | llvm-svn: 119754
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-32/+20
| | | | llvm-svn: 119740
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-151-647/+1
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-261-8/+6
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* PPC doesn't supported VLA with large alignment. This wasDale Johannesen2010-07-301-2/+2
| | | | | | | | formerly rejected by the FE, so asserted in the BE; now the FE only warns, so we treat it as a legitimate fatal error in PPC BE. This means the test for the feature won't pass, so it's xfail'd. llvm-svn: 109892
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-2/+2
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-031-4/+2
| | | | | | slots so it's always false. llvm-svn: 107550
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-14/+12
| | | | llvm-svn: 105344
* cleanupRafael Espindola2010-06-021-134/+0
| | | | llvm-svn: 105322
* The PPC MFCR instruction implicitly uses all 8 of the CRDale Johannesen2010-05-201-8/+4
| | | | | | | | | | | | | | registers. Currently it is not so marked, which leads to VCMPEQ instructions that feed into it getting deleted. If it is so marked, local RA complains about this sequence: vreg = MCRF CR0 MFCR <kill of whatever preg got assigned to vreg> All current uses of this instruction are only interested in one of the 8 CR registers, so redefine MFCR to be a normal unary instruction with a CR input (which is emitted only as a comment). That avoids all problems. 7739628. llvm-svn: 104238
* Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe whatBill Wendling2010-05-141-1/+1
| | | | | | | | | the variable actually tracks. N.B., several back-ends are using "HasCalls" as being synonymous for something that adjusts the stack. This isn't 100% correct and should be looked into. llvm-svn: 103802
* Make naked functions work on PPC.Dale Johannesen2010-04-291-1/+7
| | | | llvm-svn: 102657
* Implement -disable-non-leaf-fp-elim which disable frame pointer eliminationEvan Cheng2010-04-211-1/+1
| | | | | | | optimization for non-leaf functions. This will be hooked up to gcc's -momit-leaf-frame-pointer option. rdar://7886181 llvm-svn: 101984
* EnablePPC64RS and EnablePPC32RS are used in multiple files, so theyDan Gohman2010-04-151-3/+7
| | | | | | can't be static. llvm-svn: 101377
* Fix a bunch of namespace polution.Dan Gohman2010-04-151-8/+8
| | | | llvm-svn: 101376
* remove the MMI pointer from MachineFrameInfo.Chris Lattner2010-04-051-5/+5
| | | | llvm-svn: 100415
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-2/+2
| | | | llvm-svn: 100214
* Make isInt?? and isUint?? template specializations of the generic versions. ThisBenjamin Kramer2010-03-291-14/+16
| | | | | | | makes calls a little bit more consistent and allows easy removal of the specializations in the future. Convert all callers to the templated functions. llvm-svn: 99838
* get MMI out of the label uniquing business, just go to MCContextChris Lattner2010-03-141-2/+2
| | | | | | to get unique assembler temporary labels. llvm-svn: 98489
* Now that DBG_LABEL is updated, we can finally make MachineMove Chris Lattner2010-03-141-15/+13
| | | | | | contain an MCSymbol instead of a label index. llvm-svn: 98482
* change the DBG_LABEL MachineInstr to always be createdChris Lattner2010-03-141-2/+4
| | | | | | with an MCSymbol instead of an immediate. llvm-svn: 98481
* Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach2010-03-091-1/+1
| | | | | | | | | | is preparatory to having PEI's scavenged frame index value reuse logic properly distinguish types of frame values (e.g., whether the value is stack-pointer relative or frame-pointer relative). No functionality change. llvm-svn: 98086
* This should have gone in with 26015, see comments there.Dale Johannesen2010-02-121-0/+12
| | | | llvm-svn: 96020
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-2/+2
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* Rename the PerformTailCallOpt variable to GuaranteedTailCallOpt to reflectDan Gohman2010-02-081-6/+6
| | | | | | its current purpose. llvm-svn: 95564
* Do not store R31 into the caller's link area on PPC.Dale Johannesen2009-11-241-2/+1
| | | | | | | | | | | | This violates the ABI (that area is "reserved"), and while it is safe if all code is generated with current compilers, there is some very old code around that uses that slot for something else, and breaks if it is stored into. Adjust testcases looking for current behavior. I've verified that the stack frame size is right in all testcases, whether it changed or not. 7311323. llvm-svn: 89811
* Make capitalization of names starting "is" more consistent.Dale Johannesen2009-11-241-29/+29
| | | | | | No functional change. llvm-svn: 89724
* Add a bool flag to StackObjects telling whether they reference spillDavid Greene2009-11-121-4/+7
| | | | | | | | | | | | | slots. The AsmPrinter will use this information to determine whether to print a spill/reload comment. Remove default argument values. It's too easy to pass a wrong argument value when multiple arguments have default values. Make everything explicit to trap bugs early. Update all targets to adhere to the new interfaces.. llvm-svn: 87022
* Modify how the prologue encoded the "move" information for the FDE. GCCBill Wendling2009-11-101-31/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | generates a sequence similar to this: __Z4funci: LFB2: mflr r0 LCFI0: stmw r30,-8(r1) LCFI1: stw r0,8(r1) LCFI2: stwu r1,-80(r1) LCFI3: mr r30,r1 LCFI4: where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other things are. We generated something more like this: Leh_func_begin1: mflr r0 stw r31, 20(r1) stw r0, 8(r1) Llabel1: stwu r1, -80(r1) Llabel2: mr r31, r1 Note that we are missing the "mr" instruction. This patch makes it more like the GCC output. llvm-svn: 86729
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-5/+8
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* Simplify RegScavenger::FindUnusedReg.Jakob Stoklund Olesen2009-08-181-1/+1
| | | | | | | | | - Drop the Candidates argument and fix all callers. Now that RegScavenger tracks available registers accurately, there is no need to restict the search. - Make sure that no aliases of the found register are in use. This was a potential bug. llvm-svn: 79369
* Add support for the PowerPC 64-bit SVR4 ABI.Tilmann Scheller2009-08-151-13/+108
| | | | | | | | | | | | | | | | | The Link Register is volatile when using the 32-bit SVR4 ABI. Make it possible to use the 64-bit SVR4 ABI. Add non-volatile registers for the 64-bit SVR4 ABI. Make sure r2 is a reserved register when using the 64-bit SVR4 ABI. Update PPCFrameInfo for the 64-bit SVR4 ABI. Add FIXME for 64-bit Darwin PPC. Insert NOP instruction after direct function calls. Emit official procedure descriptors. Create TOC entries for GlobalAddress references. Spill 64-bit non-volatile registers to the correct slots. Only custom lower VAARG when using the 32-bit SVR4 ABI. Use simple VASTART lowering for the 64-bit SVR4 ABI. llvm-svn: 79091
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