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path: root/llvm/lib/Target/PowerPC/PPCInstrInfo.h
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* [NFC] [PowerPC] Add isPredicable for basic instrsQiu Chaofan2020-01-101-2/+0
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-1/+1
* [PowerPC] [Peephole] fold frame offset by using index form to save add.czhengsz2019-10-251-0/+10
* Prune two MachineInstr.h includes, fix up depsReid Kleckner2019-10-191-1/+1
* Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjointChangpeng Fang2019-09-261-2/+1
* [TargetInstrInfo] Let findCommutedOpIndices take const MachineInstr&Simon Pilgrim2019-09-251-1/+1
* [MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCountJames Molloy2019-09-211-20/+8
* Revert "[MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduce...Mitch Phillips2019-09-201-8/+20
* [MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCountJames Molloy2019-09-201-20/+8
* [PowerPC][NFC] Make `getDefMIPostRA` publicKai Luo2019-07-251-5/+5
* [PowerPC][NFC] Added `getDefMIPostRA` methodKai Luo2019-07-251-0/+5
* [PowerPC][NFC] use opcode instead of MachineInstr for instrHasImmForm().Chen Zheng2019-07-241-1/+1
* [PowerPC] Implement the areMemAccessesTriviallyDisjoint hookQingShan Zhang2019-07-021-0/+16
* [PowerPC] Enable MachinePipeliner for P9 with -ppc-enable-pipelinerJinsong Ji2019-06-111-0/+28
* Include what you use in PPCInstrInfo.hDmitri Gribenko2019-06-031-1/+0
* [PowerPC] Remove UseVSXRegStefan Pintilie2019-03-261-8/+18
* [PowerPC] fix killed/dead flag after convert x-form to d-form tranformation.Chen Zheng2019-03-051-5/+17
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [PowerPC] Remove the implicit use of the register if it is replaced by ImmQingShan Zhang2018-12-281-0/+2
* [PowerPC][NFC] Fix bugs in r+r to r+i conversionNemanja Ivanovic2018-10-221-1/+2
* [PowerPC] Remove self-copies in pre-emit peepholeNemanja Ivanovic2018-10-091-0/+10
* [PowerPC] [NFC] Refactor code for printing register operandsNemanja Ivanovic2018-09-271-0/+19
* Test commit: remove trailing whitespaceJosh Stone2018-09-111-1/+1
* [PowerPC] Add a peephole post RA to transform the inst that fed by addQingShan Zhang2018-08-201-6/+40
* [PowerPC] Infrastructure work. Implement getting the opcode for a spill in on...Stefan Pintilie2018-03-261-9/+20
* Re-commit: [MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda2018-03-231-7/+0
* Revert [MachineLICM] This reverts commit rL327856Zaara Syeda2018-03-191-0/+7
* [MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda2018-03-191-7/+0
* [PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversionNemanja Ivanovic2017-12-291-0/+2
* [PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic2017-12-151-0/+52
* [PowerPC] Remove redundant TOC savesZaara Syeda2017-11-271-0/+2
* [PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.Tony Jiang2017-11-201-0/+3
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* [PowerPC] Eliminate sign- and zero-extensions if already sign- or zero-extendedHiroshi Inoue2017-10-161-0/+15
* [PowerPC] define target hook isReallyTriviallyReMaterializable()Lei Huang2017-06-211-0/+2
* [PowerPC] Eliminate integer compare instructions - vol. 2Nemanja Ivanovic2017-05-311-0/+1
* Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-211-1/+1
* Revert r301040 "X86: Don't emit zero-byte functions on Windows"Hans Wennborg2017-04-211-1/+1
* X86: Don't emit zero-byte functions on WindowsHans Wennborg2017-04-211-1/+1
* Make TargetInstrInfo::isPredicable take a const reference, NFCKrzysztof Parzyszek2017-03-031-1/+1
* [Power9] Part-word VSX integer scalar loads/stores and sign extend instructionsNemanja Ivanovic2016-10-041-0/+17
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-141-2/+2
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-1/+1
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-141-2/+4
* TargetInstrInfo: add virtual function getInstSizeInBytesSjoerd Meijer2016-07-291-1/+1
* TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFCSjoerd Meijer2016-07-281-1/+1
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-151-1/+1
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-20/+16
* Pass DebugLoc and SDLoc by const ref.Benjamin Kramer2016-06-121-8/+8
* [PPC, SSP] Support PowerPC Linux stack protection.Tim Shen2016-04-191-0/+3
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