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path: root/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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* Remove 3 includes from MCInstrDesc.h and explicitly include them where neededPete Cooper2015-05-151-0/+1
* Add VSX Scalar loads and stores to the PPC back endNemanja Ivanovic2015-05-071-1/+12
* Add Hardware Transactional Memory (HTM) SupportKit Barton2015-03-251-0/+53
* Disabling warnings for MSVC build to enable /W4 use.Andrew Kaylor2015-03-241-2/+1
* Remove the need to cache the subtarget in the PowerPC TargetRegisterInfoEric Christopher2015-03-121-1/+1
* [PowerPC] Add support for the QPX vector instruction setHal Finkel2015-02-251-0/+42
* [PowerPC] Support non-direct-sub/superclass VSX copiesHal Finkel2015-02-161-4/+4
* [PowerPC] Put PPCEarlyReturn into its own source fileHal Finkel2015-02-011-165/+0
* [PowerPC] Put PPCVSXCopy into its own source fileHal Finkel2015-02-011-139/+0
* [PowerPC] Put PPCVSXFMAMutate into its own source fileHal Finkel2015-02-011-291/+0
* [PowerPC] Remove the PPCVSXCopyCleanup passHal Finkel2015-02-011-76/+0
* [PowerPC] Add implicit ops to conditional returns in PPCEarlyReturnHal Finkel2015-02-011-8/+13
* Use the cached subtargets and remove calls to getSubtarget/getSubtargetImplEric Christopher2015-01-301-23/+17
* Revert "r225811 - Revert "r225808 - [PowerPC] Add StackMap/PatchPoint support""Hal Finkel2015-01-141-0/+6
* Revert "r225808 - [PowerPC] Add StackMap/PatchPoint support"Hal Finkel2015-01-131-6/+0
* [PowerPC] Add StackMap/PatchPoint supportHal Finkel2015-01-131-0/+6
* [PowerPC] Split the blr definition into BLR and BLR8Hal Finkel2015-01-131-3/+5
* [PowerPC] Add a DAGToDAG peephole to remove unnecessary zero-extsHal Finkel2014-12-121-3/+5
* [PowerPC] Avoid VSX FMA mutate when killed product reg = addend regBill Schmidt2014-10-211-0/+6
* [PowerPC] Change assert to better formBill Schmidt2014-10-171-3/+3
* [PowerPC] Change liveness testing in VSX FMA mutation passBill Schmidt2014-10-171-8/+20
* Provide an implementation of getNoopForMachoTarget for PPC, otherwiseJoerg Sonnenberger2014-08-081-0/+5
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-5/+5
* add ppc64/pwr8 as targetWill Schmidt2014-06-261-1/+3
* The hazard recognizer only needs a subtarget, not a target machineEric Christopher2014-06-131-6/+8
* Remove TargetMachine from PPCInstrInfo and all dependencies andEric Christopher2014-06-121-19/+21
* Avoid using subtarget features when initializing the pass pipelineEric Christopher2014-05-221-1/+12
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final...Craig Topper2014-04-291-8/+8
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-4/+4
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-4/+4
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-211-0/+2
* [PowerPC] Add subregister classes for f64 VSX valuesHal Finkel2014-03-291-6/+27
* [PowerPC] Use a small cleanup pass to remove VSX self copiesHal Finkel2014-03-271-0/+74
* [PowerPC] Don't remove self VSX copies in PPCInstrInfo::copyPhysRegHal Finkel2014-03-271-9/+13
* [PowerPC] Select between VSX A-type and M-type FMA instructions just before RAHal Finkel2014-03-251-0/+263
* [PowerPC] Correct commutable indices for VSX FMA instructionsHal Finkel2014-03-251-0/+15
* [PowerPC] Update comment re: VSX copy-instruction selectionHal Finkel2014-03-241-2/+4
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-8/+9
* [PowerPC] Initial support for the VSX instruction setHal Finkel2014-03-131-0/+199
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-1/+1
* Add CR-bit tracking to the PowerPC backend for i1 valuesHal Finkel2014-02-281-70/+121
* Replace PPC instruction-size code with MCInstrDesc getSizeHal Finkel2014-02-021-13/+6
* Handle spilling the PPC GPRC_NOR0 register classHal Finkel2014-01-281-4/+8
* Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth2014-01-071-1/+1
* Allow MachineCSE to coalesce trivial subregister copies the same way that it ...Andrew Trick2013-12-171-2/+8
* whitespaceAndrew Trick2013-12-171-3/+3
* Improve instruction scheduling for the PPC POWER7Hal Finkel2013-12-121-2/+64
* Fix the PPC subsumes-predicate checkHal Finkel2013-12-111-0/+4
* Remove PPCScoreboardHazardRecognizerHal Finkel2013-12-021-2/+2
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-1/+4
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