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author | Hal Finkel <hfinkel@anl.gov> | 2015-02-16 23:46:30 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2015-02-16 23:46:30 +0000 |
commit | 5cedafb8cd3525b536cc6cc24a6c6841c9cd5b10 (patch) | |
tree | a6da56e8c5bd6b29f216e20b3069781831c76550 /llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | |
parent | fcb2de694ae9d8c90f4f2b989d44a621e1c35a83 (diff) | |
download | bcm5719-llvm-5cedafb8cd3525b536cc6cc24a6c6841c9cd5b10.tar.gz bcm5719-llvm-5cedafb8cd3525b536cc6cc24a6c6841c9cd5b10.zip |
[PowerPC] Support non-direct-sub/superclass VSX copies
Our register allocation has become better recently, it seems, and is now
starting to generate cross-block copies into inflated register classes. These
copies are not transformed into subregister insertions/extractions by the
PPCVSXCopy class, and so need to be handled directly by
PPCInstrInfo::copyPhysReg. The code to do this was *almost* there, but not
quite (it was unnecessarily restricting itself to only the direct
sub/super-register-class case (not copying between, for example, something in
VRRC and the lower-half of VSRC which are super-registers of F8RC).
Triggering this behavior manually is difficult; I'm including two
bugpoint-reduced test cases from the test suite.
llvm-svn: 229457
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 51d68fd14ad..d1c60a2e37c 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -699,7 +699,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, // legalization. Promote them here. const TargetRegisterInfo *TRI = &getRegisterInfo(); if (PPC::F8RCRegClass.contains(DestReg) && - PPC::VSLRCRegClass.contains(SrcReg)) { + PPC::VSRCRegClass.contains(SrcReg)) { unsigned SuperReg = TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); @@ -708,7 +708,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, DestReg = SuperReg; } else if (PPC::VRRCRegClass.contains(DestReg) && - PPC::VSHRCRegClass.contains(SrcReg)) { + PPC::VSRCRegClass.contains(SrcReg)) { unsigned SuperReg = TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass); @@ -717,7 +717,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, DestReg = SuperReg; } else if (PPC::F8RCRegClass.contains(SrcReg) && - PPC::VSLRCRegClass.contains(DestReg)) { + PPC::VSRCRegClass.contains(DestReg)) { unsigned SuperReg = TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass); @@ -726,7 +726,7 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB, SrcReg = SuperReg; } else if (PPC::VRRCRegClass.contains(SrcReg) && - PPC::VSHRCRegClass.contains(DestReg)) { + PPC::VSRCRegClass.contains(DestReg)) { unsigned SuperReg = TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass); |