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path: root/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
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* [PowerPC] Add support for vmsumudmAhsan Saghir2020-06-221-0/+4
* [PowerPC][NFC] Rename record instructions to use _rec suffix instead of oJinsong Ji2020-01-061-35/+35
* [PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0Kang Zhang2019-12-281-1/+3
* [PowerPC] Exploit `vrl(b|h|w|d)` to perform vector rotationKai Luo2019-12-231-1/+13
* [PowerPC] Fix %llvm.ppc.altivec.vc* loweringJim Lin2019-12-161-4/+4
* [PowerPC] Exploitate the Vector Integer Average InstructionsQingShan Zhang2019-12-111-0/+19
* [PowerPC] Implement the vector extend sign instruction pattern matchQingShan Zhang2019-11-221-0/+6
* Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Matt Arsenault2019-09-191-3/+3
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-3/+3
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-3/+3
* [PowerPC] Exploit single instruction load-and-splat for word and doublewordNemanja Ivanovic2019-09-171-3/+3
* [PowerPC] Exploit the vector min/max instructionsNemanja Ivanovic2019-06-061-0/+26
* Set useful flags for vector imm setting instructionsJinsong Ji2019-03-121-1/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [PowerPC] Enhance the selection(ISD::VSELECT) of vector typeZi Xuan Wu2018-11-141-0/+14
* [PowerPC] Revert commit r339779Nemanja Ivanovic2018-08-271-4/+0
* [PowerPC] Enhance the selection(ISD::VSELECT) of vector typeNemanja Ivanovic2018-08-151-0/+4
* [PowerPC] fix incorrect vectorization of abs() on POWER9Hiroshi Inoue2018-04-211-14/+0
* [PowerPC] Infrastructure work. Implement getting the opcode for a spill in on...Stefan Pintilie2018-03-261-12/+12
* [PowerPC][NFC] Explicitly state types on FP SDAG patterns in anticipation of ...Lei Huang2018-03-121-11/+13
* Adds code to PPC ISEL lowering to recognize byte inserts from vector_shuffles...Graham Yiu2017-11-061-1/+6
* Adds code to PPC ISEL lowering to recognize half-word inserts from vector_shu...Graham Yiu2017-11-011-4/+12
* [Power9] Exploit vector absolute difference instructions on Power 9Stefan Pintilie2017-08-021-0/+15
* CodeGen: Power: Add lowering for shifts of v1i128.Kyle Butt2017-05-171-0/+8
* [PPC] Move the combine "a << (b % (sizeof(a) * 8)) -> (PPCshl a, b)" to the b...Tim Shen2017-05-121-6/+34
* [PowerPC][Altivec] Add vnot extended mnemonicNemanja Ivanovic2017-02-071-0/+1
* [PowerPC][Altivec] Add vmr extended mnemonicNemanja Ivanovic2017-01-311-0/+3
* [PPC] cleanup of mayLoad/mayStore flags and memory operands.Sean Fertile2017-01-261-2/+2
* [AMDGPU, PowerPC, TableGen] Fix some Clang-tidy modernize and Include What Yo...Eugene Zelenko2016-12-091-3/+3
* [PPC] limit line width to 80 charactersEhsan Amiri2016-11-181-1/+2
* [Power9] Add patterns for vnegd, vnegwEhsan Amiri2016-11-181-2/+7
* [PowerPC] Add remaining vector permute builtins in altivec.h - LLVM portionNemanja Ivanovic2016-11-111-4/+20
* Add a blank line for a test commit.Sean Fertile2016-11-111-0/+1
* [PowerPC] Implement vector shift builtins - llvm portionNemanja Ivanovic2016-11-011-2/+4
* [PPC] add absolute difference altivec instructions and matching intrinsicsNemanja Ivanovic2016-10-311-0/+11
* Implement vector count leading/trailing bytes with zero lsb and vector parityNemanja Ivanovic2016-10-281-7/+14
* [Power9] Part-word VSX integer scalar loads/stores and sign extend instructionsNemanja Ivanovic2016-10-041-0/+16
* [Power9] Builtins for ELF v.2 API conformance - back end portionNemanja Ivanovic2016-09-271-27/+20
* [Power9] Implement new altivec instructions: bcd* seriesChuang-Yu Cheng2016-03-281-0/+58
* [Power9] Implement new altivec instructions: permute, count zero, extend sign...Chuang-Yu Cheng2016-03-261-0/+61
* [Power9] Implement new vector compare, extract, insert instructionsKit Barton2016-03-011-0/+65
* Fix for PR 26193Nemanja Ivanovic2016-02-051-1/+1
* [PPC] Implement vmrgew and vmrgow instructionsKit Barton2015-06-251-0/+50
* LLVM support for vector quad bit permute and gather instructions through buil...Nemanja Ivanovic2015-06-111-1/+3
* This patch adds support for the vector quadword add/sub instructions introducedKit Barton2015-05-251-0/+17
* [PPC64] Add vector pack/unpack support from ISA 2.07Bill Schmidt2015-05-161-0/+35
* This patch adds ABI support for v1i128 data type.Kit Barton2015-05-051-0/+11
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-6/+6
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-6/+6
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-6/+6
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