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* This patch addresses a PPC64 ELF issue with passing parameters consisting ofBill Schmidt2012-10-251-21/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | structs having size 3, 5, 6, or 7. Such a struct must be passed and received as right-justified within its register or memory slot. The problem is only present for structs that are passed in registers. Previously, as part of a patch handling all structs of size less than 8, I added logic to rotate the incoming register so that the struct was left- justified prior to storing the whole register. This was incorrect because the address of the parameter had already been adjusted earlier to point to the right-adjusted value in the storage slot. Essentially I had accidentally accounted for the right-adjustment twice. In this patch, I removed the incorrect logic and reorganized the code to make the flow clearer. The removal of the rotates changes the expected code generation, so test case structsinregs.ll has been modified to reflect this. I also added a new test case, jaggedstructs.ll, to demonstrate that structs of these sizes can now be properly received and passed. I've built and tested the code on powerpc64-unknown-linux-gnu with no new regressions. I also ran the GCC compatibility test suite and verified that earlier problems with these structs are now resolved, with no new regressions. llvm-svn: 166680
* Add in support for getIntPtrType to get the pointer type based on the ↵Micah Villmow2012-10-241-1/+2
| | | | | | | | | address space. This checkin also adds in some tests that utilize these paths and updates some of the clients. llvm-svn: 166578
* This is another TLC patch for separating code for the Darwin and ELF ABIsBill Schmidt2012-10-231-185/+449
| | | | | | | | | | | | | | | | | | | | | for the PowerPC target, and factoring the results. This will ease future maintenance of both subtargets. PPCTargetLowering::LowerCall_Darwin_Or_64SVR4() has grown a lot of special-case code for the different ABIs, making maintenance difficult. This is getting worse as we repair errors in the 64-bit ELF ABI implementation, while avoiding changes to the Darwin ABI logic. This patch splits the routine into LowerCall_Darwin() and LowerCall_64SVR4(), allowing both versions to be significantly simplified. I've factored out chunks of similar code where it made sense to do so. I also performed similar factoring on LowerFormalArguments_Darwin() and LowerFormalArguments_64SVR4(). There are no functional changes in this patch, and therefore no new test cases have been developed. Built and tested on powerpc64-unknown-linux-gnu with no new regressions. llvm-svn: 166480
* This patch fixes failures in the SingleSource/Regression/C/uint64_to_floatUlrich Weigand2012-10-181-1/+46
| | | | | | | | | | | | | | | | | | test case on PowerPC caused by rounding errors when converting from a 64-bit integer to a single-precision floating point. The reason for this are double-rounding effects, since on PowerPC we have to convert to an intermediate double-precision value first, which gets rounded to the final single-precision result. The patch fixes the problem by preparing the 64-bit integer so that the first conversion step to double-precision will always be exact, and the final rounding step will result in the correctly-rounded single-precision result. The generated code sequence is equivalent to what GCC would generate. When -enable-unsafe-fp-math is in effect, that extra effort is omitted and we accept possible rounding errors (just like GCC does as well). llvm-svn: 166178
* This patch addresses PR13949.Bill Schmidt2012-10-161-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the PowerPC 64-bit ELF Linux ABI, aggregates of size less than 8 bytes are to be passed in the low-order bits ("right-adjusted") of the doubleword register or memory slot assigned to them. A previous patch addressed this for aggregates passed in registers. However, small aggregates passed in the overflow portion of the parameter save area are still being passed left-adjusted. The fix is made in PPCTargetLowering::LowerCall_Darwin_Or_64SVR4 on the caller side, and in PPCTargetLowering::LowerFormalArguments_64SVR4 on the callee side. The main fix on the callee side simply extends existing logic for 1- and 2-byte objects to 1- through 7-byte objects, and correcting a constant left over from 32-bit code. There is also a fix to a bogus calculation of the offset to the following argument in the parameter save area. On the caller side, again a constant left over from 32-bit code is fixed. Additionally, some code for 1, 2, and 4-byte objects is duplicated to handle the 3, 5, 6, and 7-byte objects for SVR4 only. The LowerCall_Darwin_Or_64SVR4 logic is getting fairly convoluted trying to handle both ABIs, and I propose to separate this into two functions in a future patch, at which time the duplication can be removed. The patch adds a new test (structsinmem.ll) to demonstrate correct passing of structures of all seven sizes. Eight dummy parameters are used to force these structures to be in the overflow portion of the parameter save area. As a side effect, this corrects the case when aggregates passed in registers are saved into the first eight doublewords of the parameter save area: Previously they were stored left-justified, and now are properly stored right-justified. This requires changing the expected output of existing test case structsinregs.ll. llvm-svn: 166022
* This patch addresses PR13947.Bill Schmidt2012-10-111-0/+8
| | | | | | | | | | | | | | | | | | | | | | For function calls on the 64-bit PowerPC SVR4 target, each parameter is mapped to as many doublewords in the parameter save area as necessary to hold the parameter. The first 13 non-varargs floating-point values are passed in registers; any additional floating-point parameters are passed in the parameter save area. A single-precision floating-point parameter (32 bits) must be mapped to the second (rightmost, low-order) word of its assigned doubleword slot. Currently LLVM violates this ABI requirement by mapping such a parameter to the first (leftmost, high-order) word of its assigned doubleword slot. This is internally self-consistent but will not interoperate correctly with libraries compiled with an ABI-compliant compiler. This patch corrects the problem by adjusting the parameter addressing on both sides of the calling convention. llvm-svn: 165714
* Create enums for the different attributes.Bill Wendling2012-10-091-1/+2
| | | | | | | We use the enums to query whether an Attributes object has that attribute. The opaque layer is responsible for knowing where that specific attribute is stored. llvm-svn: 165488
* PR12716: PPC crashes on vector compareAdhemerval Zanella2012-10-081-1/+3
| | | | | | | | | | | | | | | | | | Vector compare using altivec 'vcmpxxx' instructions have as third argument a vector register instead of CR one, different from integer and float-point compares. This leads to a failure in code generation, where 'SelectSETCC' expects a DAG with a CR register and gets vector register instead. This patch changes the behavior by just returning a DAG with the vector compare instruction based on the type. The patch also adds a testcase for all vector types llvm defines. It also included a fix on signed 5-bits predicates printing, where signed values were not handled correctly as signed (char are unsigned by default for PowerPC). This generates 'vspltisw' (vector splat) instruction with SIM out of range. llvm-svn: 165419
* Add floating-point to and from integer conversionAdhemerval Zanella2012-10-081-0/+4
| | | | | | | This patch add altivec support for v4i32 to v4f32 and for v4f32 to v4i32 vector rounding conversion. llvm-svn: 165409
* Move TargetData to DataLayout.Micah Villmow2012-10-081-1/+1
| | | | llvm-svn: 165402
* This patch splits apart PPCISelLowering::LowerFormalArguments_Darwin_Or_64SVR4Bill Schmidt2012-10-051-24/+302
| | | | | | | into separate versions for the Darwin and 64-bit SVR4 ABIs. This will facilitate doing more major surgery on the 64-bit SVR4 ABI in the near future. llvm-svn: 165336
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-261-1/+1
| | | | | | | The hasFnAttr method has been replaced by querying the Attributes explicitly. No intended functionality change. llvm-svn: 164725
* Specify MachinePointerInfo as refering to the argument value and offset of theRoman Divacky2012-09-241-3/+5
| | | | | | | store when handling byval arguments. Thus preventing reordering of the store with load with post-RA scheduler. llvm-svn: 164553
* Small structs for PPC64 SVR4 must be passed right-justified in registers.Bill Schmidt2012-09-191-47/+128
| | | | | | | | | | | | | | | lib/Target/PowerPC/PPCISelLowering.{h,cpp} Rename LowerFormalArguments_Darwin to LowerFormalArguments_Darwin_Or_64SVR4. Rename LowerFormalArguments_SVR4 to LowerFormalArguments_32SVR4. Receive small structs right-justified in LowerFormalArguments_Darwin_Or_64SVR4. Rename LowerCall_Darwin to LowerCall_Darwin_Or_64SVR4. Rename LowerCall_SVR4 to LowerCall_32SVR4. Pass small structs right-justified in LowerCall_Darwin_Or_64SVR4. test/CodeGen/PowerPC/structsinregs.ll New test. llvm-svn: 164228
* Fix the isLocalCall() by checking for linker weakness as well.Roman Divacky2012-09-181-1/+2
| | | | llvm-svn: 164155
* Optimize local func calls to not emit nop for TOC restoration.Roman Divacky2012-09-181-2/+10
| | | | | | Patch by Adhemerval Zanella. llvm-svn: 164138
* Fix PR11985Michael Liao2012-09-121-2/+2
| | | | | | | | | | | - BlockAddress has no support of BA + offset form and there is no way to propagate that offset into machine operand; - Add BA + offset support and a new interface 'getTargetBlockAddress' to simplify target block address forming; - All targets are modified to use new interface and X86 backend is enhanced to support BA + offset addressing. llvm-svn: 163743
* PPCISelLowering.cpp: Fix r162725.NAKAMURA Takumi2012-08-301-1/+5
| | | | | | | | [Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good! Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good. llvm-svn: 162916
* PPCISelLowering.cpp: Whitespace.NAKAMURA Takumi2012-08-301-1/+1
| | | | llvm-svn: 162915
* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-281-0/+15
| | | | | | | | | Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. llvm-svn: 162764
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-281-8/+14
| | | | | | | | | | | | | | | | The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. llvm-svn: 162725
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-8/+7
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky2012-08-241-0/+16
| | | | | | In collaboration with Adhemerval Zanella. llvm-svn: 162562
* Fix typo and grammar. By Adhemerval Zanella.Roman Divacky2012-08-161-1/+1
| | | | llvm-svn: 162032
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-041-1/+3
| | | | | | | | On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. llvm-svn: 161302
* Target option DisableJumpTables is a gross hack. Move it to TargetLowering ↵Evan Cheng2012-07-021-10/+17
| | | | | | instead. llvm-svn: 159611
* Add support for the PPC isel instruction.Hal Finkel2012-06-221-5/+31
| | | | | | | The isel (integer select) instruction is supported on the 440 and A2 embedded cores and on the POWER7. llvm-svn: 159045
* Convert the PPC backend to use the new FMA infrastructure.Hal Finkel2012-06-221-2/+23
| | | | | | | The existing contraction patterns are replaced with fma/fneg. Overall functionality should be the same. llvm-svn: 158955
* Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel2012-06-201-7/+2
| | | | llvm-svn: 158823
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-191-1/+9
| | | | | | PPC will now generate STWUX and friends. llvm-svn: 158698
* Enable ILP scheduling for all nodes by default on PPC.Hal Finkel2012-06-101-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | Over the entire test-suite, this has an insignificantly negative average performance impact, but reduces some of the worst slowdowns from the anti-dep. change (r158294). Largest speedups: SingleSource/Benchmarks/Stanford/Quicksort - 28% SingleSource/Benchmarks/Stanford/Towers - 24% SingleSource/Benchmarks/Shootout-C++/matrix - 23% MultiSource/Benchmarks/SciMark2-C/scimark2 - 19% MultiSource/Benchmarks/MiBench/automotive-bitcount/automotive-bitcount - 15% (matrix and automotive-bitcount were both in the top-5 slowdown list from the anti-dep. change) Largest slowdowns: MultiSource/Benchmarks/McCat/03-testtrie/testtrie - 28% MultiSource/Benchmarks/mediabench/gsm/toast/toast - 26% MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan - 21% SingleSource/Benchmarks/CoyoteBench/lpbench - 20% MultiSource/Applications/d/make_dparser - 16% llvm-svn: 158296
* PPC32 uses R2 as the TLS register. Fix the copy and paste.Roman Divacky2012-06-051-3/+3
| | | | llvm-svn: 158004
* Implement local-exec TLS on PowerPC.Roman Divacky2012-06-041-1/+26
| | | | llvm-svn: 157935
* Enable generating PPC pre-increment (r+imm) instructions by default.Hal Finkel2012-06-041-5/+3
| | | | | | | It seems that this no longer causes test suite failures on PPC64 (after r157159), and often gives a performance benefit, so it can be enabled by default. llvm-svn: 157911
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-11/+19
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* effectively back out my last change (r155190)Gabor Greif2012-04-201-2/+2
| | | | llvm-svn: 155195
* fix obviously bogus (IMO) operand index of the load in assertsGabor Greif2012-04-201-3/+3
| | | | | | | | | (load only has one operand) and smuggle in some whitespace changes too NB: I am obviously testing the water here, and believe that the unguarded cast is still wrong, but why is the getZExtValue of the load's operand tested against zero here? Any review is appreciated. llvm-svn: 155190
* Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-19/+19
| | | | | | since they are equivalent. llvm-svn: 155186
* zap tabsGabor Greif2012-04-191-7/+7
| | | | llvm-svn: 155128
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-041-14/+3
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* Implement the SVR4 byval alignment for aggregates. Fixing a FIXME.Roman Divacky2012-04-021-1/+10
| | | | llvm-svn: 153876
* Enable prefetch generation on PPC64.Hal Finkel2012-04-011-0/+3
| | | | llvm-svn: 153851
* Set the default PPC node scheduling preference to ILP (for the embedded cores).Hal Finkel2012-04-011-0/+9
| | | | | | | The 440 and A2 cores have detailed itineraries, and this allows them to be fully used to maximize throughput. llvm-svn: 153845
* Fix dynamic linking on PPC64.Hal Finkel2012-03-311-8/+15
| | | | | | | | | | | | | | | | | | Dynamic linking on PPC64 has had problems since we had to move the top-down hazard-detection logic post-ra. For dynamic linking to work there needs to be a nop placed after every call. It turns out that it is really hard to guarantee that nothing will be placed in between the call (bl) and the nop during post-ra scheduling. Previous attempts at fixing this by placing logic inside the hazard detector only partially worked. This is now fixed in a different way: call+nop codegen-only instructions. As far as CodeGen is concerned the pair is now a single instruction and cannot be split. This solution works much better than previous attempts. The scoreboard hazard detector is also renamed to be more generic, there is currently no cpu-specific logic in it. llvm-svn: 153816
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-1/+1
| | | | llvm-svn: 153500
* Fix small-integer VAARG on SVR4 ABI PPC64.Hal Finkel2012-03-241-5/+17
| | | | | | | The PPC64 SVR4 ABI requires integer stack arguments, and thus the var. args., that are smaller than 64 bits be zero extended to 64 bits. llvm-svn: 153373
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-7/+7
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Convert more static tables of registers used by calling convention to ↵Craig Topper2012-03-111-4/+4
| | | | | | uint16_t to reduce space. llvm-svn: 152538
* Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper2012-03-111-12/+12
| | | | | | specific backends. llvm-svn: 152537
* Convert PowerPC to register mask operands.Roman Divacky2012-03-061-0/+6
| | | | llvm-svn: 152122
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